MP2624GL datasheet(5/45 Pages) MPS

5 / 45 page

MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG

MP2624 Rev.1.05

www.MonolithicPower.com

4/9/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

PIN FUNCTIONS

Package

Pin #

Name

Type

Description

Positive pin of the USB data line pair. DP and DM achieve USB host/charging

port detection automatically.

Power

Power input of the IC from the adapter or USB. Place a 1μF ceramic capacitor

from IN to PGND as close as possible to the IC.

PMID

Power

Internal Power Pin. Connect to the drain of the reverse-blocking MOSFET and the

drain of the high-side MOSFET. Bypass with a 4.7μF capacitor from PMID to PGND

as close as possible to the IC.

4, 14

Power

Switching node.

PGND

Power

Power ground.

VNTC

Pull-up voltage bias of the NTC comparator resistive divider for both the

feedback and the reference.

SCL

I/O

2C interface clock. Connect SCL to the logic rail through a 10kΩ resistor.

SDA

I/O

2C interface data. Connect SDA to the logic rail through a 10kΩ resistor.

VREF

PWM low-side driver output. Connect a 10μF ceramic capacitor from VREF to

AGND as close as possible to the IC.

ILIM

Programmable input current limit. A resistor is connected from ILIM to ground to

set the minimum input current limit. The actual input current limit is the lowest setting

by ILIM and I

2C.

AGND

I/O

Analog ground.

OTG

Boost mode enable control or input current limiting selection pin. The On-The-

Go is enabled through I

2C. During boost operation, OTG low suspends boost

operation. If the input is detected as the USB host, OTG is used as the input current

limiting selection pin. When OTG = high, IIN_LMT = 500mA. When OTG = low, IIN_LMT =

100mA.

BST

Bootstrap. Connect a 470nF bootstrap capacitor between BST and SW to form a

floating supply across the power switch driver to drive the power switch’s gate above

the supply voltage.

SYS

System output. Connect a 2x22μF ceramic capacitor from SYS to PGND as close

as possible to the IC.

BATT

Battery positive terminal. Connect a 2x22μF ceramic capacitor from BATT to

PGND as close as possible to the IC.

DISC

Battery disconnection control.

-------

Active low charge enable. Battery charging is enabled when the corresponding

-------

is low.

NTC

Temperature sense input. Connect a negative temperature coefficient thermistor.

Program the hot and cold temperature window with a resistor divider from VNTC to

NTC to AGND. The charge is suspended when NTC is out of range.

STAT

--------------

Indicator for charging operation.

INT

Open-drain interrupt output. INT sends the charging status, and the fault

interrupts the host.

Negative pin of the USB date line pair. DM and DP achieve USB host/charging

port detection automatically.

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