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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MP2624GL датащи(PDF) 29 Page - Monolithic Power Systems |
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MP2624GL датащи(HTML) 29 Page - Monolithic Power Systems |
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29 / 45 page  MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG MP2624 Rev.1.05 www.MonolithicPower.com 29 4/9/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Data line stable; data valid Change of data allowed SDA SCL Figure 16: Bit Transfer on the I 2C Bus All the transactions begin with a START (S) and can be terminated by a STOP (P). A high to low transition on the SDA line while the SCL line is high defines a START condition. A low to high transition on the SDA line when the SCL line is high defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition; it is considered free after the STOP condition (see Figure 17). SDA SCL START (S) STOP (P) Figure 17: START and STOP Conditions Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the SCL line low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL line (see Figure 18). Figure 18: Data Transfer on the I 2C BUS |
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