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TLE9255WLC датащи(PDF) 8 Page - Infineon Technologies AG |
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TLE9255WLC датащи(HTML) 8 Page - Infineon Technologies AG |
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8 / 100 page ![]() Data Sheet 8 Rev. 1.02 2018-02-02 TLE9255W Pin Configuration 4RxD Receive Data Output; “low” while a dominant signal is on the HS CAN bus, output voltage adapted to the voltage on the VIO level shift input 5 VIO Level Shift Input; reference voltage for the digital input and output pins, 100 nF decoupling capacitor to GND is recommended 6MISO SPI Serial Data Output; tri-state while CSN is “high” 7INH Inhibit Output; open drain output to control external circuitry 8SCLK SPI Clock Input; integrated pull-down current source to GND 9WAKE Wake-up Input; local wake-up input, terminated against GND and VBAT, wake-up input sensitive to signal changes in both directions 10 VBAT Battery Supply Voltage; 100 nF decoupling capacitor to GND is recommended 11 MOSI SPI Serial Data Input; integrated pull-down current source to GND 12 CANL Low-level HS CAN Bus Line 13 CANH High-level HS CAN Bus Line 14 CSN SPI Chip Select Not Input; integrated pull-up current source to VIO PAD - Connect to PCB heat sink area. Do not connect to other potential than GND. Table 1 Pin definitions and functions (cont’d) Pin Symbol Function |
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