LTC2435-1IGN datasheet(27/40 Pages) LINER

27 / 40 page

LTC2435/LTC2435-1

24351fa

APPLICATIO S I FOR ATIO

tance driving IN+ or IN–. When FO is driven by an external

oscillator with a frequency fEOSC (external conversion

clock operation), the typical differential input resistance is

3.3 • 1012/fEOSCΩ and each ohm of source resistance

driving IN+ or IN– will result in 0.15 • 10–6 • fEOSC ppm +FS

gain error. The effect of the source resistance on the two

input pins is additive with respect to this gain error. The

typical +FS and –FS errors as a function of the sum of the

source resistance seen by IN+ and IN– for large values of

CIN are shown in Figures 18 and 19.

In addition to this gain error, an offset error term may also

appear. The offset error is proportional to the mismatch

between the source impedance driving the two input pins

IN+ and IN– and with the difference between the input and

reference common mode voltages. While the input drive

circuit nonzero source impedance combined with the

converter average input current will not degrade the INL

performance, indirect distortion may result from the modu-

lation of the offset error by the common mode component

of the input signal. Thus, when using large CIN capacitor

values, it is advisable to carefully match the source imped-

ance seen by the IN+ and IN– pins. When FO = LOW

(internal oscillator and 60Hz notch), every 1Ω mismatch

in source impedance transforms a full-scale common

mode input signal into a differential mode input signal of

0.023ppm. When FO = HIGH (internal oscillator and 50Hz

notch), every 1Ω mismatch in source impedance trans-

forms a full-scale common mode input signal into a

differential mode input signal of 0.02ppm. When FO is

driven by an external oscillator with a frequency fEOSC,

every 1Ω mismatch in source impedance transforms a

full-scale common mode input signal into a differential

mode input signal of 0.15 • 10–6 • fEOSCppm. Figure 20

shows the typical offset error due to input common mode

voltage for various values of source resistance imbalance

between the IN+ and IN– pins when large CIN values are

used.

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

The magnitude of the dynamic input current depends upon

the size of the very stable internal sampling capacitors and

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by IN+ and

IN–, the expected drift of the dynamic current, offset and

Figure 18. +FS Error vs RSOURCE

at IN+ or IN– (Large CIN)

Figure 19. –FS Error vs RSOURCE

at IN+ or IN– (Large CIN)

Figure 20. Offset Error vs Common Mode

Voltage (VINCM = VIN+ = VIN–) and Input

Source Resistance Imbalance (∆RIN =

RSOURCEIN+ – RSOURCEIN–) for Large CIN

Values (CIN ≥ 1µF)

RSOURCE (Ω)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

2435 F18

400

800

1200

1600

2000

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 3.75V

VIN– = 1.25V

FO = GND

TA = 25°C

CIN = 1µF, 10µF

CIN = 0.01µF

CIN = 0.1µF

RSOURCE (Ω)

100

2435 F19

400

800

1200

1600

2000

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 1.25V

VIN– = 3.75V

FO = GND

TA = 25°C

CIN = 1µF, 10µF

CIN = 0.01µF

CIN = 0.1µF

VINCM (V)

–310

–320

–330

–340

–350

–360

–370

–380

2435 F20

2.0

5.0

1.0

3.0

4.0

0.5

2.5

1.5

3.5

4.5

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = VIN– = VINCM

A: ∆RIN = 1k

B: ∆RIN = 500Ω

C: ∆RIN = 200Ω

D: ∆RIN = 0Ω

E: ∆RIN = –200Ω

F: ∆RIN = –500Ω

G: ∆RIN = –1k

FO = GND

TA = 25°C

CIN = 10µF

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