LTC2435-1IGN datasheet(25/40 Pages) LINER

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LTC2435/LTC2435-1

24351fa

APPLICATIO S I FOR ATIO

Driving the Input and Reference

The input and reference pins of the LTC2435/LTC2435-1

converters are directly connected to a network of sampling

capacitors. Depending upon the relation between the

differential input voltage and the differential reference

voltage, these capacitors are switching between these

four pins transferring small amounts of charge in the

process. A simplified equivalent circuit is shown in

Figure 14.

For a simple approximation, the source impedance RS

driving an analog input pin (IN+, IN–, REF+ or REF–) can be

considered to form, together with RSW and CEQ (see

Figure 14), a first order passive network with a time

constant τ = (RS + RSW) • CEQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

When using the internal oscillator (FO = LOW or HIGH), the

LTC2435’s front-end switched-capacitor network is clocked

at 76800Hz corresponding to a 13µs sampling period and

the LTC2435-1’s front end is clocked at 69900Hz corre-

sponding to 14.2µs. Thus, for settling errors of less than

1ppm, the driving source impedance should be chosen

such that τ ≤ 13µs/14 = 920ns (LTC2435) and τ <14.2µs/

14 = 1.01µs (LTC2435-1). When an external oscillator of

frequency fEOSC is used, the sampling period is 2/fEOSC

and, for a settling error of less than 1ppm, τ ≤ 0.14/fEOSC.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

the INL performance of the converter. Figure 14 shows the

mathematical expressions for the average bias currents

flowing through the IN+ and IN– pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 15. The CPAR capacitor

includes the LTC2435/LTC2435-1 pin capacitance (5pF

typical) plus the capacitance of the test fixture used to

obtain the results shown in Figures 16 and 17. A careful

implementation can bring the total input capacitance (CIN

+ CPAR) closer to 5pF thus achieving better performance

than the one predicted by Figures 16 and 17. For simplic-

ity, two distinct situations can be considered.

For relatively small values of input capacitance (CIN <

0.01µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

for CIN will deteriorate the converter offset and gain

performance without significant benefits of signal filtering

and the user is advised to avoid them. Nevertheless, when

small values of CIN are unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the

LTC2435/LTC2435-1 can maintain their exceptional accu-

racy while operating with relative large values of source

resistance as shown in Figures 16 and 17. These mea-

sured results may be slightly different from the first order

approximation suggested earlier because they include the

effect of the actual second order input network together

with the nonlinear settling process of the input amplifiers.

For small CIN values, the settling on IN+ and IN– occurs

almost independently and there is little benefit in trying to

match the source impedance for the two pins.

Larger values of input capacitors (CIN > 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

When FO = LOW (internal oscillator and 60Hz notch), the

typical differential input resistance is 22MΩ (LTC2435) or

24MΩ (LTC2435-1) which will generate a +FS gain error

of approximately 0.023ppm (LTC2435) or 0.021ppm

(LTC2435-1) for each ohm of source resistance driving

IN+ or IN–. For the LTC2435, when FO = HIGH (internal

oscillator and 50Hz notch), the typical differential input

resistance is 26MΩ which will generate a +FS gain error of

approximately 0.019ppm for each ohm of source resis-

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