LTC2435-1IGN datasheet(22/40 Pages) LINER

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LTC2435/LTC2435-1

24351fa

HIGH). If FO is driven by an external oscillator of frequency

fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before

time tEOCtest, the device returns to the sleep state. The

conversion result is held in the internal static shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins on

this first rising edge of SCK and concludes after the 24th

rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of the

conversion result on the 24th rising edge of SCK. After the

24th rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 24th rising edge of

SCK, see Figure 12. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 24 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2435/LTC2435-1 internal

pull-up at pin SCK is disabled. Normally, SCK is not

externally driven if the device is in the internal SCK timing

mode. However, certain applications may require an exter-

nal driver on SCK. If this driver goes Hi-Z after outputting

a LOW signal, the LTC2435/LTC2435-1 internal pull-up

remains disabled. Hence, SCK remains LOW. On the next

falling edge of CS, the device is switched to the external

SCK timing mode. By adding an external 10k pull-up

resistor to SCK, this pin goes HIGH once the external driver

goes Hi-Z. On the next CS falling edge, the device will

remain in the internal SCK timing mode.

APPLICATIO S I FOR ATIO

Figure 12. Internal Serial Clock, Reduced Data Output Length

SDO

SCK

(INTERNAL)

>tEOCtest

MSB

SIG

BIT 8

TEST EOC

BIT 19

BIT 18

BIT 20

BIT 21

BIT 22

EOC

BIT 23

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA OUTPUT

CONVERSION

SLEEP

2435 F12

<tEOCtest

VCC

10k

TEST EOC

VCC

REF+

REF–

SCK

IN+

IN–

SDO

GND

214

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2435/

LTC2435-1

= 50Hz REJECTION (LTC2435)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2435)

= 50Hz/60Hz REJECTION (LTC2435-1)

VCC

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