LTC2435-1IGN datasheet(20/40 Pages) LINER

20 / 40 page

LTC2435/LTC2435-1

24351fa

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 1ms after VCC exceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or

external. SCK must be driven LOW prior to the end of POR

in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion is over. On the falling edge of

EOC, the conversion result is loaded into an internal static

shift register. Data is shifted out the SDO pin on each

falling edge of SCK enabling external circuitry to latch data

on the rising edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 24th falling edge of SCK, SDO

goes HIGH (EOC = 1) indicating a new conversion has

begun.

APPLICATIO S I FOR ATIO

Figure 9. External Serial Clock, Reduced Data Output Length

SDO

SCK

(EXTERNAL)

DATA OUTPUT

CONVERSION

SLEEP

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

2435 F09

MSB

SIG

BIT 8

BIT 19

BIT 9

BIT 20

BIT 21

BIT 22

EOC

BIT 23

BIT 0

EOC

Hi-Z

TEST EOC

VCC

REF+

REF–

SCK

IN+

IN–

SDO

GND

214

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

1µF

2.7V TO 5.5V

LTC2435/

LTC2435-1

= 50Hz REJECTION (LTC2435)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2435)

= 50Hz/60Hz REJECTION (LTC2435-1)

VCC

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 11.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the conversion is over.

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