ATECC508A datasheet(45/109 Pages) MICROCHIP

45 / 109 page

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Upon completion of a command execution from 1 to 32 bytes of command, results are available to

be read inside a group of 4 to 35 bytes.

Any attempt to read beyond the end of the valid output buffer returns 0xFF to the system, and the

address counter does not wrap around to the beginning of the buffer.

There may be situations where the system may wish to re-read the output buffer, for example when the

CRC check reveals an error. In this case, the host should send a two-byte sequence to the ATECC508A

consisting of the correct device address and a word address of 0x00 (Reset, per Table 6-2), followed by

a Stop condition. This causes the address counter to be reset to zero and permits the data to be rewritten

(or re-read) to (or from) the device. This address reset sequence does not prohibit subsequent read

operations if data were available for reading in the I/O Buffer prior to the sequence execution.

After one or more read operations to retrieve the results of a command execution, the first write operation

resets the address counter to the beginning of the I/O Buffer.

6.7

SMBus Timeout

The ATECC508A supports the SMBus Timeout feature in which the ATECC508A will reset its serial

interface and release the SMBus (i.e. stop driving the bus and let SDA float high) if the SCL pin is held

low for more than the minimum tTIMEOUT specification. The ATECC508A will be ready to accept a new

Start condition before tTIMEOUT maximum has elapsed.

Figure 6-5. SMBus Timeout

SCL

TIMEOUT (MAX)

TIMEOUT (MIN)

Device will release bus and

be ready to accept a new

Start condition within this time.

6.8

I2C Synchronization

It is possible for the system to lose synchronization with the I/O port on the ATECC508A, perhaps due a

system reset, I/O noise, or other condition. Under this circumstance, the ATECC508A may not respond as

expected, may be asleep, or may be transmitting data during an interval when the system is expecting to

send data. To resynchronize, the following procedure should be followed:

To ensure an I/O channel reset, the system should send the standard I2C software reset sequence,

as follows:

–

A Start bit condition.

–

Nine cycles of SCL, with SDA held high.

–

Another Start bit condition.

–

A Stop bit condition.

It should then be possible to send a read sequence, and if synchronization has completed

properly, the ATECC508A will ACK the device address. The device may return data or may

leave the bus floating (which the system will interpret as a data value of 0xFF) during the data

periods.

ATECC508A

I2C Interface

Datasheet Complete

DS20005927A-page 45

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