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ATECC508A датащи(PDF) 44 Page - Microchip Technology

номер детали ATECC508A
подробное описание детали  Cryptographic Co-processor with Secure Hardware-Based Key Storage
PDF  109 Pages
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производитель  MICROCHIP [Microchip Technology]
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ATECC508A датащи(HTML) 44 Page - Microchip Technology

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6.5
I2C Transmission from the ATECC508A
When the ATECC508A is awake and not busy, the bus master can retrieve the current buffer contents
from the device using an I2C Read. If valid command results are available, the size of the group returned
is determined by the particular command which has been run (see Section Security Commands);
otherwise, the size of the group (and the first byte returned) will always be four: count, status/error, and 2-
byte CRC. The bus timing is shown in Figure 8-3.
Table 6-3. I2C Transmission from the ATECC508A
Name
I2C Name
Direction Description
Device
Address
Device
Address
To slave
This byte selects a particular device on the I2C interface and ATECC508A
will be selected if bits 1 through 7 of this byte match bits 1 thru 7 of the
I2C_Address byte in the Configuration zone. Bit 0 of this byte is the
standard I2C R/W pin, and should be one to indicate that the bytes following
the device address travel from the slave to the master (Read).
Data
Data1,N
To master The output group, consisting of the count, status/error byte or the output
packet followed by the two byte CRC per Section I/O Groups.
The status, error, or command outputs can be read repeatedly by the master. Each time a Read
command is sent to the ATECC508A along the I2C interface, the device transmits the next sequential
byte in the output buffer. See the following section for details on how the device handles the address
counter.
If the ATECC508A is busy, idle, or asleep, it will NOT ACK the device address on a read sequence. If a
partial command has been sent to the device and a read sequence [Start + DeviceAddress(R/W
== R)] is sent to the device, then the ATECC508A will not ACK the device address to indicate that no
data is available to be read.
6.6
Address Counter
Writes to and/or reads from the ATECC508A I/O Buffer over the I2C interface are treated as if the device
were a FIFO. Either the I2C byte or page write/read protocols can be used. The number of bytes
transferred with each page sequence does not affect the operation of the device.
The first byte transmitted to the device is treated as the size byte. Any attempt to send more than this
number of bytes, or any attempts to write beyond the end of the I/O Buffer (71 bytes) will cause the
ATECC508A to not ACK those bytes.
After the host writes a single command byte to the input buffer, reads are prohibited until after the device
completes command execution. Attempts to read from the device prior to the last command byte being
sent will result in an ACK of the device address but all ones (0xFF) on the bus during the data intervals
because the device is still waiting for the completion of the command transmission. If the host attempts to
send a read byte after the last byte of the command has been transmitted, the device will be executing
the command and will NOT ACK the device address.
Data may be read from the device under the following three conditions:
On power-up, the single byte 0x11 (Section Status/Error Codes) can be read inside a four byte
group.
If a complete block has been received by the device, but there are any errors in parsing or
executing the command, a single byte of error code is available (also inside a four byte group).
ATECC508A
I2C Interface
© 2017 Microchip Technology Inc.
Datasheet Complete
DS20005927A-page 44



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