ATECC508A datasheet(38/109 Pages) MICROCHIP

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Note: This may result in the loss of data stored in the command output buffer.

5.2

I/O Flags

The system is always the bus master, so before any I/O transaction, the system must send an eight bit

flag to the device to indicate the I/O operation that will be subsequently performed.

Table 5-1. IO Flags

Value Name

Meaning

0x77 Command After this flag, the system starts sending a command group to the device. The first bit of the

group can follow immediately after the last bit of the flag.

0x88 Transmit

This command tells the device to wait for a bus turnaround time and then to start transmitting its

response to the previously transmitted command group.

0xBB Idle

Upon receipt of an idle flag, the device goes into the idle mode and remains there until the next

Wake token is received.

0xCC Sleep

Upon receipt of a sleep flag, the device enters the low-power sleep mode until the next Wake

token is received.

Note:

All other values are reserved and should not be used.

•

Transmit Flag: Used to turn around the bus so that the ATECC508A can send data back to the

system. The bytes that the device returns to the system depend on the current state of the device

and may include status, error code, or command results.

When the device is busy executing a command, it ignores the SDA pin and any flags that are sent

by the system. See Table 9-4 for each command type’s execution delays. The system must

observe these delays after sending a command to the device.

•

Idle Flag: Used to transition the ATECC508A to the idle mode, which causes the input/output buffer

to be flushed. It does not invalidate the contents of the TempKey and RNG Seed registers. This flag

can be sent to the device during any time that it will accept a flag. When the device is in the idle

mode, the watchdog timer is disabled.

•

Sleep Flag: Transitions the ATECC508A to the low power sleep mode, which causes a complete

reset of the device, including invalidation of the contents of the SRAM and all volatile registers. This

flag can be sent to the device at any time that it will accept a flag.

5.3

Synchronization

Since the communications protocol is half-duplex, there is the possibility that the system and the

ATECC508A will fall out of synchronization with each other. In order to speed recovery, the device

implements a timeout that forces it to sleep under certain circumstances.

5.3.1

I/O Timeout

After a leading transition for any data token has been received, the ATECC508A will expect both the

completion of the token and the start of the next (if this is not the last token of the group) to be properly

received by the device within the tTIMEOUT interval. Failure to send enough bits, or the transmission of an

illegal token (e.g. a low pulse exceeding tZLO), will cause the device to enter the Sleep mode after the

tTIMEOUT interval.

ATECC508A

Single-Wire Interface

Datasheet Complete

DS20005927A-page 38

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