ATECC508A datasheet(40/109 Pages) MICROCHIP

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I2C Interface

The I2C Interface uses the SDA and SCL pins to indicate various I/O states to the ATECC508A. This

interface is designed to be compatible at the protocol level with the Microchip AT24C16 Serial EEPROM

operating at 1 MHz.

Note: There are many differences between the two devices (for example, the ATECC508A and

AT24C16 have different default I2C addresses); therefore, designers should read the respective data

sheets carefully.

The SDA pin is normally pulled high with an external pull-up resistor because the ATECC508A includes

only an open-drain driver on its output pin. The bus master may either be open-drain or totem pole. In the

latter case, it should be tri-stated when the ATECC508A is driving results on the bus. The SCL pin is an

input and must be driven both high and low at all times by an external device or resistor.

6.1

I/O Conditions

The device responds to the following I/O conditions:

6.1.1

Device is Asleep

When the device is asleep, it ignores all but the Wake condition.

•

Wake: if SDA is held low for a period of greater than tWLO, the device will exit low power mode and

after a delay of tWHI, it will be ready to receive I2C commands. The device ignores any levels or

transitions on the SCL pin when the device is idle or asleep and during tWLO. At some point during

tWHI the SCL pin is enabled and the conditions listed in Section Device is Awake are honored.

The Wake condition requires that either the system processor manually drives the SDA pin low for tWLO,

or a data byte of 0x00 be transmitted at a clock rate sufficiently slow so that SDA is low for a minimum

period of tWLO. When the device is awake, the normal processor I2C hardware and/or software can be

used for device communications up to and including the I/O sequence required, thus putting the device

back into low power (i.e. sleep) mode.

When there are multiple ATECC508A devices on the bus, and the I2C interface is run at 133 kHz or

slower, the transmission of certain data patterns (such as 0x00) will cause all the ATECC508A devices

on the bus to wake-up. Because subsequent device addresses transmitted along the bus will only match

the desired devices, the unused devices will remain idle and not cause any bus conflicts.

In the I2C mode, the device will ignore a wake sequence that is sent when the device is already awake.

6.1.2

Device is Awake

When the device is awake, it honors the conditions listed below:

•

DATA Zero: if SDA is low and stable while SCL goes from low to high to low, then a zero bit is

being transferred on the bus. SDA can change while SCL is low.

•

DATA One: if SDA is high and stable while SCL goes from low to high to low, then a one bit is being

transferred on the bus. SDA can change while SCL is low.

ATECC508A

I2C Interface

Datasheet Complete

DS20005927A-page 40

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