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TMS320VC5471GHKA датащи(PDF) 95 Page - Texas Instruments

номер детали TMS320VC5471GHKA
подробное описание детали  Fixed-Point Digital Signal Processor
PDF  97 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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TMS320VC5471GHKA датащи(HTML) 95 Page - Texas Instruments

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Electrical Specifications
86
June 2001 – Revised December 2002
SPRS180C
Table 6–40. SPI Rising Edge Timing Requirements
MIN
NOM
MAX
UNIT
td(ENRS–CLKH)
Delay time, Rising enable start active to first clock high
A – 3†
A†
A + 3†
ns
td(CLKL–ENRE)
Delay time, Last clock low to rising enable end
A/2 – 3†
A/2†
A/2 + 3†
ns
tw(ENRT)
Pulse duration, Rising enable toggle
A – 3†
A†
A + 3†
ns
td(CLKL–DOV)
Delay time, Clock low to data out valid
2
8
ns
tsu(DIV–CLKH)
Setup time, Data in valid to clock high
6
ns
th(CLKH–DIIV)
Hold time, Clock high to data in invalid
4
ns
† A = 4 x PTV x tc(ARM)
In this mode, all timing related activity for Data In and Enable is based on the falling edge of the SPI Clock.
The timing activity for Data Out will be based on the rising edge of the SPI clock.
MSB
LSB
Bit=31
Bit=32–total
MCUENO, 1 2,
(negative edge
triggered)
MCUENO, 1 2,
(positive edge
triggered)
(negative level
triggered)
MCUENO, 1 2,
MCUENO, 1 2,
triggered)
(positive level
CLKX_SPI
MCUDO
MCUDI
MSB
LSB
Bit=total–1
Bit=0
td(ENRS–CLKH)
td(CLKL–ENRE)
tw(ENRT)
th(CLKH–DIIV)
tsu(DIV–CLKH)
td(CLKL–DOV)
tc(SPI)
tw(SPI–H)
tw(SPI–L)
tr(SPI)
tf(SPI)
Figure 6–38. SPI Rising Edge Timings



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