TMS320VC5471GHKA datasheet(93/97 Pages) TI

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Electrical Specifications

June 2001 – Revised December 2002

SPRS180C

6.16 SPI Clock Timings

SPI timings are derived from the internal SPI clock. This clock is only available externally during a serial

transfer.

Table 6–38 through Table 6–40 assume testing over recommended operating conditions (see Figure 6–37

and Figure 6–38).

Table 6–38. SPI Clock Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(SPI)

Cycle time, CLKX_SPI

168.4

A†

tw(SPI–H)

Pulse duration, CLKX_SPI high

A/2 – 3†

A/2†

A/2 + 3†

tw(SPI–L)

Pulse duration, CLKX_SPI low

A/2 – 3†

A/2†

A/2 + 3†

tr(SPI)

Rise time, SPI output signals.

CLKX_SPI, MCUDO, MCUEN0,

MCUEN1, and MCUEN2

tf(SPI)

Fall time, SPI output signals.

CLKX_SPI, MCUDO, MCUEN0,

MCUEN1, and MCUEN2

† A = 4 x PTV x tc(ARM)

Table 6–39. SPI Falling Edge Timing Requirements

MIN

NOM

MAX

UNIT

td(ENFS–CLKH)

Delay time, Falling enable start active to first clock high

A/2 – 3†

A/2†

A/2 + 3†

td(CLKL–ENFE)

Delay time, Last clock low to falling enable end

A – 3†

A†

A + 3†

tw(ENFT)

Pulse duration, Falling enable toggle

A – 3†

A†

A + 3†

td(CLKH–DOV)

Delay time, Clock high to data out valid

tsu(DIV–CLKL)

Setup time, Data in valid to clock low

th(CLKL–DIIV)

Hold time, Clock low to data in invalid

† A = 4 x PTV x tc(ARM)

In this mode, all timing related activity for Data In and Enable is based on the falling edge of the SPI Clock.

The timing activity for Data Out will be based on the rising edge of the SPI clock.

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