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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8976 датащи(PDF) 32 Page - Wolfson Microelectronics plc |
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WM8976 датащи(HTML) 32 Page - Wolfson Microelectronics plc |
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32 / 83 page  WM8976 Preliminary Technical Data w PTD Rev 2.0 February 2005 32 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 ADCVOL [7:0] 11111111 ( 0dB ) ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB R15 ADC Digital Volume 8 ADCVU Not latched ADC volume does not update until a 1 is written to ADCVU Table 18 ADC Digital Volume Control INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8976 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its static level. Figure 15 Input Peak Limiter Operation In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. |
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