WM8976 datasheet(19/83 Pages) WOLFSON

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Preliminary Technical Data

WM8976

PTD Rev 2.0 February 2005

pora

DGND

Internal POR active

Device Ready

No Power

por_off

Power Supply

POR

I2S Clocks

ADC Internal

State

midrail_on

Analogue Inputs

ADCDAT pin

ADCEN bit

Power down

Init

Normal Operation

Init

Power down

ADC enabled

ADC off

adcint

DNC

INPPGAEN bit

adcint

INPPGA enabled

DNC

POR

POR Undefined

VMID enabled

VMIDSEL/

BIASEN bits

AVDD/2

midrail_off

(Note 1)

(Note 2)

(Note 3)

(Note 4)

por_on

Figure 9 ADC Power Up and Down Sequence (not to scale)

SYMBOL

MIN

TYPICAL

MAX

UNIT

tmidrail_on

300

tmidrail_off

tadcint

2/fs

n/fs

ADC Group Delay

29/fs

n/fs

Table 3 Typical ADC Power Up and Down Sequence

Notes:

The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This

time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance

and AVDD power supply rise time.

The analogue input pin discharge time, tmidrail_off, is determined by the VMID pin discharge time.

This time is dependent upon the value of VMID decoupling capacitor and VMID pin input

resistance and AVDD power supply decay time. The time, tmidrail_off, is measured using a 1µF

capacitor and will vary dependent upon the value of input coupling capacitor.

The timings tmidrail_on and tmidrail_off are measured using a 1µF capacitor and will vary dependent

upon the value of input coupling capacitor. The measurements were taken at 10% and 90%

points on the charge time curve.

While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system

noise but no significant digital output will be present.

The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for

normal ADC operation.

ADCDAT data output delay from power up - with power supplies starting from 0V - is determined

primarily by the VMID charge time. ADC initialisation and power management bits may be set

immediately after POR is released; VMID charge time will be significantly longer and will dictate

when the device is stabilised for analogue input.

ADCDAT data output delay at power up from device standby (power supplies already applied) is

determined by ADC initialisation time, 2/fs.

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