LC823450 datasheet(86/112 Pages) ONSEMI

номер детали	LC823450

подробное описание детали	Low Power & High-Resolution Audio Processing System LSI

PDF	112 Pages

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производитель	ONSEMI [ON Semiconductor]

домашняя страница	http://www.onsemi.com

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LC823450

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High−Speed DDR Mode

Figure 33. High−Speed DDR Mode

Clock

(from LSI)

In put

(to LSI)

Out put

(from LSI)

t ODLY(max)

tODLY(min)

tPP

tTHL

t TLH

t ISU

t IH

t ISU

t IH

t ODLY(max)

t ODLY(min)

• [Applied pin]

♦ Clock

: SDCLK0, SDCLK1, SDCLK2

♦ Output : SDCMD0, SDCMD1, SDCMD2,

SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] output

♦ Input

: SDCMD0, SDCMD1, SDCMD2,

SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] input

Table 50.

I/O Voltage

(VDDSD0, VDDSD1, VDDSD2)

2.7 V to 3.6 V

1.7 V to 1.95 V

Unit

External Load

10 pF to 40 pF

10 pF to 30 pF

10 pF to 23 pF

I/O Drivability

8 mA

10 mA

8 mA

6 mA

Item

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Clock Frequency

fPP

MHz

Clock rise time

tTLH

−

Clock fall time

tTHL

−

INPUT CMD

Input set−up time

(from SD to LSI)

tISU

7.0

−

7.4

−

7.7

−

10.2

−

Input hold−up time

(from SD to LSI)

tIH

0.7

−

0.6

−

0.8

−

OUTPUT CMD

Output Delay time

(from LSI to SD)

tODLY

3.1

20.5

3.1

20.5

3.1

21.1

3.1

24.1

INPUT DAT

Input set−up time

(from SD to LSI)

tISU

7.1

−

7.4

−

7.7

−

10.7

−

Input hold−up time

(from SD to LSI)

tIH

1.3

−

1.4

−

1.4

−

OUTPUT DAT

Output Delay time

(from LSI to SD)

tODLY

2.6

17.8

2.6

17.6

2.6

18.5

2.6

22.2

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