LC823450 datasheet(53/112 Pages) ONSEMI

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LC823450

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Table 18. RECOMMENDED OPERATING CONDITIONS

Item

Symbol

Function

Low Voltage Operation

High Voltage Operation

Unit

Xtal Input

Frequency

Fxin1

System,

Audio clock

(XT1 oscillator)

12 MHz or 20 MHz

tolerance :

±200 ppm or less

Jitter :

±50 ps or less

(Note 38)

12 MHz or 20 MHz or

24 MHz or 48 MHz

tolerance :

±200 ppm or

less

Jitter :

±50 ps or less

(Note 38)

−

FxinRTC

RTC clock

(XTRTC oscillator)

32.768 kHz

Jitter :

±500 ps or less

Same as left

−

Frc

(RC oscillator)

0.4

(Note 39)

Same as left

MHz

Time for

Xtal Stable

Txin1

(Note 41)

Same as left

TxinRTC

1000

(Note 41)

Same as left

Internal Clock

Frequency

Farm

Cortex−M3

100

160

(Note 40)

MHz

Fahb

AHB

100

160

(Note 40)

MHz

Fapb

APB

100

160

(Note 40)

MHz

Fdsp

DSP

100

160

(Note 40)

MHz

Faud

(Note 35)

AUDCLK(768fs)

33.8688

147.456

Same as left

MHz

Fdec

DECCLK(Note 36)

(MP3 Decoder)

16.9344

73.728

Same as left

MHz

Fenc

ENCCLK(Note 37)

(MP3 Encoder)

8.4672

36.864

Same as left

MHz

35. Audio blocks run on 256 * Fs (sampling frequency) clock.

However, Class−D AMP, etc run on 384 * Fs (sampling frequency).

These clocks are generated from 768 * Fs (Base Clock) divided by 3 and 2 respectively.

36. MP3 Decoder runs on clock of 384 * Fs (sampling frequency of MPEG1 mode).

It runs on the clock of the same frequency as MPEG1 mode during MPEG2 / 2.5 mode. For example, even when operating in MPEG 2 / 2.5

mode (Fs = 22.05 / 11.025 KHz as an example), please supplies 16.9344 MHz(= 384 * 44.1 kHz) clock which is the same clock frequency

as MPEG1 mode.

37. MP3 Encoder runs on clock of 192 * Fs(sampling frequency of MPEG1 mode).

It runs on the clock of the same frequency as MPEG1 mode during MPEG2 / 2.5 mode. For example, even when operating in MPEG2 / 2.5

mode (Fs = 22.05 / 11.025 KHz as an example), please supplies 8.4672 Mhz (= 192 * 44.1 kHz) clock which is the same clock frequency

as MPEG1 mode.

38. Refer to the detailed datasheet. If USB function is not used, the specification required may be relaxed. Please contact our representative

in detail.

39. Vdd1 = 0.93 V to 1.27 V, Ta = −20

_C to 65_C.

40. When Farm, Fdsp are over 100 MHz, 1 * Wait is required for Cortex−M3 and LPDSP32 to access internal ROM by the register described

in the ProgrammersModel_SystemController as memory access control register4.

41. These are just reference values under Ta = 25

_C, and need to be adjusted to customer board situation.

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