LC823450 datasheet(64/112 Pages) ONSEMI

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LC823450

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Table 28. 10BIT ADC CONVERTER CHARACTERISTIC (continued)

(TA = 25°C, VDD1 = 1.2 V, AVDDADC = 3.0 V, FVIN = 1 kHz (Note 42))

Item

Applied

Unit

Max

Typ

Min

Condition

Symbol

While it Stabilizes of Ladder

(Resumption Time)

Tstr

−

(Note 2)

0 Scale Offset Voltage (Transit

Voltage from 0 to 1)

VZT

(Note 47)

Typ−20

VRL +

(VRH−VRL)/

1024

Typ +20

AN[5:0]

Full−scale Offset Voltage (Transit

Voltage from 1022 to 1023)

VFST

(Note 47)

Typ−20

VRH −

(VRH−VRL)/

1024

Typ +20

AN[5:0]

Differential Linearity Error

DNL

(Note 48)

−1.5

−

+1.5

LSB

AN[5:0]

Linearity Error

INL

(Note 48)

−2.0

−

+2.0

LSB

AN[5:0]

*Each electrical specification is the results of simulation.

42. Each electrical characteristic is specified under the condition which VR terminal is connected with analog ground through 0.1

μF decoupling

capacitor and the voltage is independently supplied to VRH and VRL.

43. A normal conversion result is not obtained immediately after the power supply turning on and immediately after the return from the state of

the power down. The time to get a normal performance depends on the state of the terminal VR as shown in the following table.

For example, it takes about 2 ms until a normal conversion result can be obtained when VR terminal is connected with analog ground through

0.1

μF decoupling capacitor.

Terminal VR

TSTR

Decoupled

1.0 ms

× CREF × 0.047 μF

Not Decoupled

(Include no VR Terminal)

μs

44. Between VRH and VRL

45. The terminal VR is decoupled.

46. The terminal VR is not decoupled (include no VR terminal)

47. VZT, VFST depend on analog driver output impedance(Rimp) of AN[5:0]

Rimp(

VZT

VFST

Min

Typ

Max

Min

Typ

Max

1000

typ − 20

VRL+(VRH−VRL)/1024

typ + 20

typ − 20

VRH−(VRH−VRL)/1024

typ + 20

10000

typ − 32

VRL+(VRH−VRL)/1024

typ + 20

typ − 20

VRH−(VRH−VRL)/1024

typ + 25

100000

typ − 125

VRL+(VRH−VRL)/1024

typ + 20

typ − 35

VRH−(VRH−VRL)/1024

typ + 65

48. 1LSB = (VFST−VZT)/1022 , INLn = ((1LSB x n+VZT)−Vn)/1LSB , DNLn = (Vn+1−Vn)/1LSB−1

INL depends on analog driver output impedance(Rimp) of AN[5:0]

49. Tstc(ADC sample holding time) must satisfy following formula, too.

Tstc > tA ( Tstc = (1/Fc)

× Ns )

♦ Fc: Frequency of reference clock of ADC(AD_CLK).

Refer to ADC specifications for the method of generating AD_CLK.

♦ Ns: Fadcsmpl + 1.

fADCSMPL can be set by the register. Refer to ADC specifications.

♦ tA: Time decided by output impedance (Rimp) of analog input driver of AN[5:0] (value of tA)

− In case of VR terminal is decoupled

Figure 8.

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