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Data Sheet

AD9993

Rev. A | Page 17 of 56

SPI CONFIGURATION PROGRAMMING

The SPI_CONFIG register controls AD9993 SPI interface

operation. By default, the SPI bus operates MSB first. In MSB

fist mode, the register address counter decrements automati-

cally during multiple byte reads or writes. The SPI bus can be

configured to run LSB first by setting the SPI_LSB_FIRSTx bits

to 1. During LSB first multiple register read or write operations,

the register address counter is incremented automatically. SPI

registers can be reset to their Reset values by setting the self

clearing SPI_SOFT_RESETx bits to 1.

Changes to the writeable SPI registers labeled transfer in Table 10

do not take effect immediately when written to the device via

the SPI. Values are held in a shadow register set until the self

clearing CHIP_REGMAP_TRANSFER bit in the DEVICE_

UPDATE register is set. All changes to transfer register values

then take effect simultaneously.

ADC REGISTER UPDATE INDEXING

In addition to the register transfer mechanism, the POWER_

MODES and FLEX_OUTPUT_MODE registers have an

indexing mechanism. Each of the four ADC cores has its own

page containing these registers. These pages can be

programmed independently or simultaneously in any

combination. ADC core register sets are addressed for a

particular register map master/slave transfer by setting the

SPI_ADC_x_INDEX bits in the DEVICE_INDEX register.

these bits set when the next transfer occurs.

ADCs

The MxFE ADCs are multistage pipelined CMOS ADC cores

designed for use in communications receivers.

ADC ARCHITECTURE

The AD9993 architecture consists of a dual front-end sample-

and-hold circuit, followed by a pipelined switched capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result.

The input stage of each ADC core contains a differential

sampling circuit that can be ac- or dc-coupled in differential or

single-ended modes.

Input Common-Mode Voltage (VCM) References

The analog inputs of the AD9993 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. Four

on-board common-mode voltage references are included in the

design, one for each AD9993 ADC, and are available from the

A_CML, B_CML, C_CML, and D_CML pins. Using these

common-mode voltage outputs to set the input common mode

of each ADC is recommended. Optimum performance is

achieved when the common-mode voltage of the analog input is

set by the on-chip common mode references. The A_CML,

B_CML, C_CML, and D_CML pins must be decoupled to

ground by a 0.1 μF capacitor.

ADC SECTION PROGRAMMING

Each of the four ADCs ha

s its power mode programmed by

the indexed ADC_PDWN_MODE bit field of the POWER_

MODES register (see the ADC Register Update Indexing

section). At reset, all four ADC cores are in power-down mode.

ADC digital data output modes are programmed by the indexed

FLEX_OUTPUT_MODE register (see the ADC Register Update

Indexing section). Setting the DP_OUT_DATA_EN_N bit to 0

enables the data output of each ADC selected in the DEVICE_

INDEX register. At reset, ADC output data is disabled. Setting

the DP_OUT_DATA_INV bit to 1 inverts the data output from

selected ADCs. The DP_OUT_DFS bit field selects the output

code for each selected ADC, offset binary (twos complement with

the sine bit inverted), twos complement (reset value), or gray code.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9993 is a differential switched

capacitor circuit that has been designed for optimum

performance while processing a differential input signal.

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 22. To bias the

analog input, the VCM voltage can be connected to the center tap

of the secondary winding of the transformer.

Figure 22. Differential Transformer-Coupled Configuration

Differential double balun coupling is used as the input

configuration for AD9993 ADC performance characterization

(see Figure 23). In this configuration, the input is ac-coupled and

the VCM voltage is provided to each input through a 33 Ω resistor.

These resistors compensate for losses in the input baluns to

provide a 50 Ω impedance to the driver.

2V p-p

49.9Ω

0.1µF

ADC

x_VINP

x_VINN x_CML

0.1µF

33Ω

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