AD9993BBCZ datasheet(41/57 Pages) AD

номер детали	AD9993BBCZ

подробное описание детали	Integrated Mixed-Signal Front End

PDF	57 Pages

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производитель	AD [Analog Devices]

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41 / 57 page

AD9993

Data Sheet

Rev. A | Page 40 of 56

CLKGEN CONTROL REGISTER

Address: 0x034, Reset: 0x04, Name: CLKGEN_CTRL2

Table 33. Bit Descriptions for CLKGEN_CTRL2

Bits

Bit Name

Description

Reset

Access

CLKGEN_DAC_M0_INV

Swaps CMOS and differential clock buffer for DAC only.

0x0

0 = normal mode.

1 = inverts CLKGEN_MODE[0] for DAC only.

CLKGEN_ADC_M0_INV

Swaps CMOS and differential clock buffer for ADC only.

0x1

0 = normal mode.

1 = inverts CLKGEN_MODE[0] for ADC only.

[1:0]

CLKGEN_MODE

Configures the IC for external or internal clock.

0x0

00 = selects on-chip synthesizer to drive LVDS at 1 GHz, ADC at 250 MHz,

and DAC at 500 MHz.

01 = same as 00 except uses differential clock buffer for DAC and ADC.

10 = selects external clock source to drive LVDS at clock rate, ADC at clock

rate divide by 4, and DAC at clock rate divide by 2. Minimum clock rate =

200 MHz.

11 = same as 10 except uses differential clock buffer for DAC and ADC.

DAC LVDS RX CONTROL REGISTER

Address: 0x035, Reset: 0x4D, Name: DAC_LVDS_CTRL

AD9993BBCZ датащи(PDF) 41 Page - Analog Devices