MFC2000 datasheet(273/426 Pages) ETC

273 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

14-7

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

T4 Line Length

(T4Halfwords)

$01FF8179

(Not Used)

Line Length bits 9-8

Rst. Value

xxxxxx00b

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

T4 Line Length

(T4Halfwords)

$01FF8178

Line Length bits 7-0

Rst. Value

00h

Read Value

00h

Bit 15-10:

Not used

Bit 9-0:

Line Length

The T4 Line Length register defines the number of bytes in the line to

be coded or decoded. Line length values from 001h through 3ffh

correspond to 1 through 1023 halfwords of data.

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

T4 Interrupt Mask

(T4IntMask)

$01FF8177

(Not Used)

Enable Wr

T4Data

FIFO Rdy

Enable Rd

T4Data FIFO

Rdy

Enable Wr

Uncoded

FIFO Rdy

Enable Rd

Uncoded

FIFO Rdy

Enable Wr

Ref FIFO

Rdy

Rst. Value

xxx00000b

Read Value:

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

T4 Interrupt Mask

(T4IntMask)

$01FF8176

Enable End

of Line

(Not Used)

Enable Line

Error

(Not Used)

Rst. Value

0xx0xxxxb

Read Value

00h

Bit 15-13:

Not used

Bit 12:

WrT4DataFIFORdy Enable Interrupt

Bit 11:

RdT4DataFIFORdy Enable Interrupt

Bit 10:

WrUncodedFIFORdy Enable Interrupt

Bit 9:

RdUncodedFIFORdy Enable Interrupt

Bit 8:

WrRefFIFORdy Enable Interrupt

Bit 7:

End of Line Enable Interrupt.

Bit 6-5:

Not used

Bit 4:

Line Error Enable Interrupt.

Bit 3-0:

Not used

The four interrupt enable bits correspond to bits in the T4 Status register. The position of each interrupt enable bit

is in the same place as its corresponding bit in the T4 Status register (bit 7 – End of Line Enable Interrupt

corresponds to bit 7 – EOL Condition).

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