MFC2000 datasheet(271/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

14-5

Bit 0:

Flush the code word.

The Flush CW bit is only valid during MMR compression mode. Writes

to this bit are ignored when coding/decoding is in progress, or when

decompression is selected. When the Flush CW bit is set at the end of

coding a line, it causes any data in the active T4Data FIFO to be filled

in order to make a complete halfword which can then be read by the

CPU or DMA controller. The fill bits are the opposite value of the last

CW bit, unless the non-inverted flush bit in the T4Config register is set.

In this case, the data is flushed with zeros. One halfword is always

output when the flush bit is set even if the last CW is already halfword

aligned.

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

T4 Status

(T4Status)

$01FF8174 (R)

T4 Datax

DMA Page

Boundary

T4 Datax

FIFO DMA

Acknowledge

T4 Datax

FIFO DMA

Request

Write

T4Datax

FIFO Ready

Read

T4Datax

FIFO Ready

Write

Uncoded

FIFO Ready

Read

Uncoded

FIFO

Ready

Write

Reference

FIFO

Ready

Rst. Value

00h

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

T4 Status

(T4Status)

$01FF8175 (R)

EOL

Condition

Tag Bit

non-

Consecutive

EOL/

MMREOL

Line Error

Line Error Type

All White

Line

Rst. Value

00h

Read Value

00h

Bit 15:

This a copy of the hardware signal from the DMA channel indicating

when the DMA block size has been reached and is used by the FIFO

to prevent its DMA request from being asserted if Smart EOL

Operation has been enabled via the T4 Configuration register.

Bit 14:

This is a copy of the hardware signal from the DMA channel indicating

a DMA transfer is in progress.

Bit 13:

This is a copy of the hardware signal to the DMA channel indicating

the desire to initiate a DMA transfer.

Bit 12:

The WrT4DataFIFORdy bit is set during decompression mode when

the active T4Data FIFO is not full and is cleared when the FIFO is full.

Bit 11:

The RdT4DataFIFORdy bit is set when compressed data is available

in the active T4Data FIFO. This bit is cleared when there is no data

available.

Bit 10:

The WrUncodedFIFORdy bit is set during compression mode when

the Uncoded Line FIFO is not full and is cleared when the FIFO is full.

Bit 9:

The RdUncodedFIFORdy bit is set when uncompressed data is

available in the Uncoded Line FIFO. This bit is cleared when there is

no data available.

Bit 8:

The WrRefFIFORdy bit is set during either MR/MMr compression or

decompression mode when the Reference Line FIFO is not full and is

cleared when the FIFO is full.

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