MFC2000 datasheet(31/426 Pages) ETC

31 / 426 page

Multifunctional Peripheral Controller 2000

MFC2000

100723A

Conexant

4-1

4. CPU and Bus Interface

4.1

Memory Map and Chip Select Description

4.1.1

Memory Map

The ARM7TDMI Core is capable of directly accessing 4 GB of memory (A31-A0). The MFC2000 is designed to

directly access 64-MB of memory composed of internal and external memory spaces by means of the 26-bit

system address bus (A25-A0). The MFC2000 internally decodes address range 00000000H-03FFFFFFH (64 M).

Address range 01000000H-01FFFFFFH (16 M) is arranged for the internal registers/memory and external

Countach Imaging DSP Subsystem memory. Address range 00000000H-00FFFFFFH (16 M) and Address range

02000000H-03FFFFFFH (32 M) are arranged for the external device/memory use on the ARM Bus. Only

24 address lines (A23-A0) are brought out of the MFC2000 chip, and the lower half and the higher half are

multiplexed through the same 12 pins. The 16 MB address range (maximum) can be decoded externally, if

necessary. Figure 4-1 and Figure 4-2 show the MFC2000 memory map with memory type designations and

locations and provides memory segmentation into select signal ranges.

4.1.1.1

Internal Memory Space

The MFC2000 internal memory occupies 128 kB of the address range from 01FE0000h through 01FFFFFh).

Internal memory space includes the following:

Cache memory space (64 kB)

(01FE0000h-01FEFFFFh)

(Reserved space) (32 kB)

(01FF0000h-01FF7FFFh)

Internal register space (4 kB)

(01FF8000h-01FF8FFFh)

Internal RAM space (28 kB)

(01FF9000h-01FFFFFFh)

The cache memory space includes the following:

The cache memory (4096 bytes)

(01FE0000h-01FE0FFFh)

The Tag memory (4096 bytes)

(01FE1000h-01FE1FFFh)

(Reserved) (56 kB)

(01FE2000h-01FEFFFFh)

The internal register address range consists of 3 sections:

The first (lowest) section (01FF8000h to 01FF87FFh, 2 kB), is reserved for operational registers, i.e., those

that are modified during normal operation, but which are not intended to require firmware initialization after

reset.

The second section (01FF8800h to 01FF8DFFh, 1.5 kB) contains the setup registers, i.e., those that are

generally written only once for system initialization after reset.

The third section (01FF8E00h to 01FF8FFFh, 512 bytes) is reserved for testing purposes.

Note:

All internal register accesses are two CPUCLK-cycle operations.

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