MFC2000 datasheet(235/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

11-3

Once the data is prepared for output by the Bit Rotation Block, it may be retrieved by the External Print ASIC via

the Bit Packer DMA channel. The BRB issues the ready signal to indicate that a halfword of data is ready for

retrieval to the DMA Controller. Then, the DMA Controller will grant the DMA channel 2 access cycle by activating

the DMAACK2 when system bus is available if DMAREQ2 is active and BRB output ready signal is active.

11.2 Block Diagram

A high-level block diagram of the Bit Rotation Block is shown. Note that the internal RAM is double-banked, so

that these operations of fetching and packing can occur simultaneously (however, they are not allowed to occur

to/from the same bank at the same time).

brb_regs

This block is used to hold the internal registers of the BRB. The registers are split into setup registers,

operation registers, and test registers. Each group has a separate chip select sent by the SIU.

brb_memif

This block has three separate interfaces: the SIU, the Swath Fetcher, and the Bit Packer. If a bit

rotation operation is in progress (rotateStart = 1 in the RotCtrl register), SIU local memory access is locked out,

and only the swath Fetcher and Bit Packer blocks may access the memory at this time. If the rotateStart bit is not

set, then the SIU has access to the 1 kB memory through locations 01FF9000h-01FF93FFh.

Swath Fetcher

This block works in conjunction with channel 3 of the DMA Controller to transfer image data from

the swath buffer to the local SRAM for Bit Rotation.

Bit Packer

This block is responsible for the actual rotation of image data. It performs this rotation by picking bits

out the local SRAM and constructing the final rotated output data for the External Print ASIC.

brbsync

The brb_regs and Swath Fetcher blocks operate at the SIUCLK frequencies, while the Bit Packer and

the brb_memif blocks operate at IHSCLK frequencies. The purpose of this block is to synchronize

communications between the internal blocks of the BRB.

Swath Fetcher

brbsync

Control,

Status , and

Data

Registers

Bit Packer

512 x 16 Local SRAM

BRB Control and

signals

Data Mux

BRB Local SRAM

Memory Controller

ipb_di[15:0]

ipb_do[15:0]

BRB local memory

access control signals

siuclk

ihsclk

resn

BRB Block

DMA control and

handshaking

signals

Figure 11-4. MFC2000 Bit Rotation Block Diagram

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