MFC2000 datasheet(236/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

11-4

Conexant

100723A

11.2.1 Swath Fetcher

The Swath Fetcher block is responsible for initiating as well as controlling the order of the transfer of data from the

swath buffer to the internal RAM of the Bit Rotation Block. There are several control signals provided to the Swath

Fetcher DMA channel for controlling what order the channel will read data out of image memory. The Fetcher

DMA will not support burst mode. This is due to the fact that in order to use burst mode, the DRAM that comprises

the image memory must be accessed using page mode. When accessing DRAM for the Bit Rotation block, the

sequential data stream rarely contains elements out of the same page of DRAM. Because of this, in most cases,

only single-access cycles can be realized when reading data out of the image memory for the Bit Rotation Block.

The order in which data is fetched out of the swath buffer depends on shuttle direction only. The way data is

fetched out of the swath buffer is best described pictorially. In the figure, each cell corresponds to a halfword (16

bits) in memory. The gray portion represents the printable image region, and a full line corresponds to the warp of

the swath buffer. The general order in which halfwords are fetched from the swath buffer is indicated by the

arrows. The starting address value that the firmware must program into the Swath Fetcher DMA channel depends

on the shuttle direction. While printing in a left-to-right fashion (when viewing the print on the page), the value

must correspond to the halfword of the upper left-hand corner of the image in the swath buffer (in the example

shown, this address would be base+6H. While printing in a right-to-left fashion, the value must correspond to the

upper right-hand corner of the image (in the figure, this would be base+AH). The value that would be programmed

in the Rotation Line Length (RotLine) register in this example would be 0005H (one less than the actual number of

bytes that comprise the image).

base+5*warp

base+3*warp

base+warp-2H

base+2H

base+CH

base+AH

base+8H

base+6H

base+4H

base+2H

base+CH

base+AH

base+8H

base+6H

base+4H

base

base+warp

base+(NG-1)*warp

base+4*warp

base+2*warp

base

base+warp

base+(NG-1)*warp

base+4*warp

base+2*warp

base+3*warp

base+5*warp

base+warp-2H

Left-to-Right

Shuttle Direction

Fetch Order

Right-to-Left

Shuttle Direction

Fetch Order

Figure 11-5. Fetcher DMA Channel Fetch Order

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