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MFC2000 датащи(PDF) 234 Page - List of Unclassifed Manufacturers |
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MFC2000 датащи(HTML) 234 Page - List of Unclassifed Manufacturers |
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234 / 426 page ![]() MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 11-2 Conexant 100723A Nozzle Example A Nozzle Example B Line 1 Line 3 Line 2 etc... Figure 11-2. Examples of Nozzle Head Configurations Because the firmware and Bi-Level Resolution Conversion block work in conjunction to remove all nozzle shift parameters, the Bit Rotation Block may always view the data in such a way that it views the nozzles as always being one column of N nozzles, where N corresponds to the number of nozzles on the inkjet head itself. In fact, the only configuration information that the Bit Rotation block needs to know is the number of nozzles on the inkjet head, the shuttle direction, the width of the line being printed, and the warp. The figure shows how the Bit Rotation Block views the swath regardless of the actual physical nozzle configuration. Line 1 Line 3 Line 2 Line N N = Number of nozzles in inkjet head Figure 11-3. Nozzle Configuration by Bit Rotation Block (Regardless of Physical Nozzle Configuration) The BRB works in conjunction with 2 DMA channels of the DMA controller. Within the MFC2000, the DMA channels used are channels 2 and 3. Channel 3 is used to “fetch” data from the external swath buffer that resides in the system’s image memory, and is referred to as the Swath Fetcher DMA channel from here on. DMA Channel 2 is used to transfer “packed” or rotated image data to the External Print ASIC, and will be referred to as the Bit Packer DMA channel from here on. The BRB uses a local memory (in the BRB block) to perform its rotation operation. Words are “fetched into the local memory, and then bits are picked out of the halfword and then “packed” or shifted into an output register, in effect, rotating the swath image data by 90 degrees. The internal buffer size within the Bit Rotation Block is 512 x 1 halfword (16 bits). This buffer is further subdivided into two separate 256 x 16 bit “banks” for reasons of system performance. While one 256 x 16-bit buffer is being operated upon, the other 256x16-bit buffer may be filled by the Fetcher DMA channel. Because of this, the system only needs to keep up with the print rate, which in the worst case scenario, is 256 bits every fire cycle if 256 nozzles are used. |
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