AD9652BBCZ-310 datasheet(27/37 Pages) AD

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AD9652

Data Sheet

Rev. B | Page 26 of 36

The calibration engine monitors any errors and resets the

calibration cycle if the input signal exceeds the input range for

1000 samples within a single calibration cycle.

At startup, when the AD9652 is first powered and a valid clock

is applied, a fast start-up background calibration is performed

and converges 64 times faster than the normal calibration cycle.

At 310 MSPS, the fast start-up calibration updates after 1.3 seconds.

The fast start-up calibration allows the AD9652 to be used

sooner than waiting for a full calibration cycle and typically

degrades SNR performance by less than 0.5 dB. This degradation

lasts until a full calibration cycle completes.

In cases where configuration of the AD9652 changes and a

recalibration is needed, a fast start-up calibration can be

initiated by an SPI register write or by asserting and

deasserting the PDWN pin.

To initiate using the SPI register, use Register 0x08[1:0]. To start

a new fast calibration, put either or both ADC channels in

standby and then return them to normal operation mode by

writing 0x2 and then 0x0 to Register 0x08[1:0]. After returning

to normal operation mode, the fast calibration is initiated one

time followed by the normal, full calibration cycle. In addition

to standby, this is also the case for power-down. Writing a 0x1

followed by a 0x0 initiates a fast calibration. Alternatively, a fast

start-up calibration can be initiated by writing 0x0C and then

0x08 to Register 0x4FB.

The PDWN pin can be configured to put the device in power-

down or standby mode based on the setting in Register 0x08[1:0].

Transitioning from either power-down or standby into normal

mode causes a fast calibration to be initiated. Configuration

changes that require a new calibration include, but are not

limited to, changes of setting for VREF, dither enable/disable,

clock input changes, and DCS state changes.

There are various advanced configuration options associated

with the background calibration for applications that require

special treatment. The options include an optional recovery

mode for standby and a pausing background calibration.

If standby is used in an application, by default, the AD9652

keeps the current corrections, but initiates a new fast calibration

when returning to normal operation mode. For standby, if

conditions have not significantly changed, the AD9652 can be

configured to retain the last correction coefficients by writing

0x00 to Register 0x4FA before entering the standby mode. This

returns the device to the same operation as when it entered

standby, retaining previous calibration values in standby mode

and continuing the normal calibration cycle when returned to

normal operation mode.

Although this is not recommended, in some instances such as

when all the environmental, clocking, and input signals are very

stable, the calibration can be paused. Pausing the background

calibration causes a slight degradation in performance, but can

be accomplished by writing 0x1 to Register 0x4FB, Bit 0. To re-

enable the background calibration, write 0x0 to Register 0x4FB,

Bit 0. Note: Register 0x4FB has reserved bits that must be

preserved when accessing that and similar registers.

DIGITAL OUTPUTS

The AD9652 output drivers are for standard ANSI LVDS, but

optionally the drive current can be reduced using Register 0x15.

The reduced drive current for the LVDS outputs potentially

reduce the digitally induced noise.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

The AD9652 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled when the device is

set for power-down mode.

Timing

The AD9652 provides latched data with a pipeline delay of

26 input sample clock cycles. Data outputs are available one

propagation delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and the corresponding

loads to reduce transients within the AD9652. These transients

can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9652 is 80 MSPS.

At clock rates below 80 MSPS, dynamic performance may

degrade.

Data Clock Output

The AD9652 also provides a data clock output (DCO) intended

for capturing the data in an external register. Figure 2 shows a

timing diagram of the AD9652 output modes. The DCO relative to

the data output can be adjusted using Register 0x17. There are 32

delay settings with approximately 81 ps per step. Data is output

in a DDR format and is aligned to the rising and falling edges of

the clock derived from DCO±.

ADC OVERRANGE

The ADC overrange (OR) indicator is asserted when an

overrange is detected on the input of the ADC. The overrange

condition is determined at the output of the ADC pipeline and,

therefore, is subject to a latency of 26 ADC clocks. An

overrange at the input is indicated by this bit, 26 clock cycles

after it occurs.

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