AD9652BBCZ-310 datasheet(36/37 Pages) AD

36 / 37 page

Data Sheet

AD9652

Rev. B | Page 35 of 36

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD9652, it

is recommended that the designer become familiar with these

guidelines, which describes the special circuit connections and

layout requirements needed for certain pins.

Powerand Ground Recommendations

When connecting power to the AD9652, it is recommended that

three separate power supplies be used. AVDD3 requires a 3.3 V

supply, AVDD_CLK and AVDD require a 1.8 V supply, and

DRVDD requires a 1.8 V supply. SPIVDD is typically connected

to the same supply as DRVDD, but can be connected to a separate

supply between 1.8 V and 3.3 V to ease the interface to the logic

device that connects to the SPI pins (CLK, SDIO, and CSB).

The AVDD3 supply must be supplied from a clean 3.3 V power

source. Decoupling must be a combination of PCB plane

capacitance and decoupling capacitors to cover both high and low

frequency noise sources. Typical capacitors of 0.1 μF and 1 μF

near the AD9652 AVDD3 pins are advised.

The AVDD and AVDD_CLK supply connection must be

powered up simultaneously to achieve proper on-chip biasing;

therefore, it is recommended to connect the two supply voltages

to a single source. Similar to the AVDD3 supply, decoupling must

be a combination of PCB plane capacitance and decoupling

capacitors to cover both high and low frequency noise sources.

Typical capacitors of 0.1 μF and 1 μF near the AD9652 AVDD

and AVDD_CLK pins is advised.

The DRVDD and SPIVDD supply connection must also have

decoupling but these can be placed slightly further away from

the AD9652. DRVDD and SPIVDD can be tied together for

applications that can use a 1.8 V SPI interface logic. Optionally,

SPIVDD can be driven with a supply of up to 3.3 V to support

higher voltage logic interfaces.

Multiple large area PCB ground planes are recommended and

provide many benefits. Low impedance power and ground

planes are needed to maintain performance. Stacking power and

ground planes in the PCB provides high frequency decoupling.

Ground planes and thermal vias help dissipate heat generated

by the device. With proper decoupling and smart partitioning

of the PCB analog, digital, and clock sections, optimum

performance is easily achieved.

VCM

The VCM pin must be decoupled to ground with a 0.1 μF

capacitor, as shown in Figure 54. For optimalchannel-to-channel

isolation, a 33 Ω resistor must be included between the AD9652

VCM pin and the Channel A analog input network connection,

as well as between the AD9652 VCM pin and the Channel B

analog input network connection.

RBIAS

The AD9652 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor sets the master current

reference of the ADC core and must have at least a 1%tolerance.

ReferenceDecoupling

Decouple the VREF pin externally to ground with a low ESR,

1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic

capacitor.

SPI Port

The SPI port must not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9652 to keep these signals from transitioning at the converter

input pins during critical sampling periods.

AD9652BBCZ-310 датащи(PDF) 36 Page - Analog Devices

AD9652BBCZ-310 датащи(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

датащи скачать

ссылки URL