AD9652BBCZ-310 datasheet(24/37 Pages) AD

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Data Sheet

AD9652

Rev. B | Page 23 of 36

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9652.

The full-scale input range can be adjusted by varying the reference

voltage via the SPI. The input span of the ADC linearly tracks

reference voltage changes.

Internal Reference Connection

A stable and accurate programmable reference is built into

the AD9652, allowing a voltage reference from 1.0 V to 1.25 V

to provide up to a 2.5 V p-p differential full-scale input. By

default the VREF voltage is set 1.25 V, but can be modified using

To configure the AD9652 for an internal reference, the SENSE

pin must be tied low. When SENSE is tied low, the ADC uses

VREF directly and provides a differential input voltage of two

times the VREF value.

To achieve optimal noise performance when using the internal

reference, it is recommended that the VREF pin be decoupled

by 1.0 μF and 0.1 μF capacitors close to the pin. Figure 57 shows

the configuration for the internal reference connection resulting

in a input voltage set by VREF, that is, a 2.5 V p-p differential

full-scale input.

VREF

VSELECT

AD9652

SELECT

LOGIC

0.1µF

1.0µF

VIN–A/VIN–B

VIN+A/VIN+B

ADC

CORE

SENSE

Figure 57. Internal Reference Configuration

If the internal reference of the AD9652 drives multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 58 shows how

the internal reference voltage is affected by loading.

–1

–2

–3

–4

02.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

LOAD CURRENT (mA)

VREF = 1.25V

Figure 58. Reference Voltage Error vs. Load Current

External Reference Operation

The use of an external reference can be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference that is

applied to the VREF pin. An internal reference buffer loads the

external reference with an equivalent 6 kΩ load. The internal

buffer generates the positive and negative full-scale references

for the ADC core. Therefore, the external reference must be

limited to a maximum of 1.25 V to maintain an input voltage of

2.5 V p-p differential full-scale input or less.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9652 sample clock

inputs, CLK+ and CLK−, with a differential signal with a high

slew rate. The signal is typically ac-coupled into the CLK+ and

CLK− pins via a transformer or via capacitors. These pins are

biased internally (see Figure 59) and require no external bias. If

the inputs are floated, the CLK− pin is intentionally biased

slightly lower than CLK+ to prevent spurious clocking (this is

not shown in Figure 59).

AVDD_CLK

CLK+

5pF

CLK–

0.9V

Figure 59. Simplified Equivalent Clock Input Circuit

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