AD9652BBCZ-310 datasheet(32/37 Pages) AD

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Data Sheet

AD9652

Rev. B | Page 31 of 36

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit

locations. The memory map is roughly divided into three

sections: the chip configuration registers (Address 0x00 to

Address 0x02); the channel index and transfer registers

(Address 0x05 and Address 0xFF); and the ADC functions

registers, including setup, control, and test (Address 0x08 to

Address 0x4FB).

The memory map register table (see Table 17) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x09,

the global clock register, has a hexadecimal default value of

0x01. This means that the LSB or Bit 0 = 1, and the remaining

bits are 0s. This setting is the default output format value, which

is twos complement. For more information on the functions

controlled by Register 0x00 to Register 0x17, see the AN-877

Application Note. This application note also details the

functions controlled by all remaining registers.

Open and Reserved Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location must be written with 0s, unless otherwise

noted. Writing to these locations is required only when part of

an address location is open (for example, Address 0x18). If the

entire address location is open/unused/undocumented (for

example, Address 0x13), this address location must not be written.

Default Values

After the AD9652 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 17.

LogicLevels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

TransferRegisterMap

The 0x08, 0x09, 0x0B, 0x0D, 0x0F, 0x10, 0x14, 0x16, 0x17, and

0x30 registers are shadowed. Writes to these addresses do not

affect device operation until a transfer command is issued by

writing 0x01 toAddress 0xFF, setting the transfer bit. This allows

these registers to be updated internally and simultaneously when

the transfer bit is set. The internal update occurs when the

transfer bit is set, and then the bit autoclears.

Channel SpecificRegisters

Some channel setup functions, such as the signal monitor

thresholds, can be programmed to a different value for each

channel. In these cases, channel address locations are internally

duplicated for each channel. These registers and bits are designated

in Table 17 as local. These local registers and bits can be accessed

by setting the appropriate Channel A or Channel B bits in

the registers of both channels. In a read cycle, only Channel A

or Channel B are set to read one of the two registers. If both bits

are set during an SPI read cycle, the device returns the value for

Channel A. Registers and bits designated as global in Table 17

affect the entire device and the channelfeatures for which

independent settings are not allowed. The settings in Register 0x05

do not affect the globalregisters and bits.

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