AD9652BBCZ-310 datasheet(26/37 Pages) AD

26 / 37 page

Data Sheet

AD9652

Rev. B | Page 25 of 36

device timing is dependent on the duty cycle of the input clock

signal. In some cases, it may be appropriate to disable the duty

cycle stabilizer, for example, if a high quality RF clock is

available to drive the AD9652 clock input and does not need

adjustment in duty cycle correction. In most other applications,

enabling the DCS circuit is recommended to maximize ac

performance.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (fIN) due to jitter (tJ) can be calculated by

SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10

)

(

SNR



]

In the equation, the rms aperture jitter represents the root-

mean-square of all jitter sources, which includes the clock

input, the analog input signal, and the ADC aperture jitter

specification. IF undersampling applications are particularly

sensitive to jitter, as shown in Figure 64.

550

500

fIN (MHz)

MEASURED

0.8ps

0.2ps

0.1ps

0.05ps

Figure 64. SNRFS vs. Input Frequency and Jitter

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9652.

Drive external clock sources and buffers from a clean ADC

output driver supply to avoid modulating the ADC clock with

noise. Low jitter, crystal controlled oscillators make the best

clock sources. If the clock is generated from another type of

source (by gating, dividing, or another method), retime it by the

original clock at the last step.

Refer to the AN-501 Application Note, Aperture Uncertainty

and ADC System Performance, and the AN-756 Application

Note, Sampled Systems and the Effects of Clock Phase Noise and

Jitter, for more information about jitter performance as it relates

to ADCs.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 65, the power dissipated by the AD9652 is

proportional to its sample rate. The data in Figure 65 was taken

using the same operating conditions as those used for the

Typical Performance Characteristics section.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

2.5

2.0

1.5

1.0

0.5

280

230

180

130

SAMPLE RATE (MSPS)

AVDD3

AVDD_CLK

DRVDD/SPIVDD

AVDD

POWER

Figure 65. Power and Current vs. Sample Rate

By asserting power-down (either through setting Register 0x08

or by asserting the PDWN pin high), the AD9652 is placed in

power-down mode. In this state, the ADC typically dissipates

less than 1 mW. During power-down, the output drivers are

placed in a high impedance state. Deasserting the PDWN pin

(forcing it low) returns the AD9652 to its normal operating

mode. Note that the level on PDWN is referenced to the digital

output driver supply (DRVDD) and cannot exceed that supply

voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI, for additional

details.

INTERNAL BACKGROUND CALIBRATION

The AD9652 uses a background calibration to continually correct

errors between internal analog circuits to maintain the high

level of noise performance over varying conditions. The calibration

correction digitally monitors the errors in the various analog

blocks, calculates the error, and applies corrections. The back-

ground correction is calculated every 3 × 233 samples; therefore,

when running at 310 MSPS, the update rate is about 83 seconds.

Each calibration cycle is independent from previous calibrations to

improve tracking. There are no requirements on the input signal

for the background calibration.

The calibration occurs independently for each ADC path. The

background calibration continually operates but does not

update if the input signal is significantly out of range (beyond

the OTR) because this can cause errors in the calibration

calculation.

AD9652BBCZ-310 датащи(PDF) 26 Page - Analog Devices

AD9652BBCZ-310 датащи(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

датащи скачать

ссылки URL