CS61884 datasheet(26/72 Pages) CIRRUS

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CS61884

DS485PP4

In host mode, TAOS is generated for a particular

channel by asserting the associated bit in the TAOS

Enable Register (03h) (See Section 14.4 on

page 35).

Since MCLK is the reference clock, it should be of

adequate stability.

9.6 Automatic TAOS

While a given channel is in the LOS condition, if

the corresponding bit in the Automatic TAOS

set, the device will drive that channel’s TTIP and

TRING with the all ones pattern. This function is

only available in host mode. Refer to Loss-of-Sig-

nal (LOS) (See Section 10.5 on page 27).

9.7 Driver Failure Monitor

In host mode, the Driver Failure Monitor (DFM)

function monitors the output of each channel and

sets a bit in the DFM Status Register (05h) (See

Section 14.6 on page 35) if a secondary short cir-

cuit is detected between TTIP and TRING. This

generates an interrupt if the respective bit in the

DFM Interrupt Enable Register (07h) (See Sec-

tion 14.8 on page 36) is also set. Any change in the

DFM Status Register (05h) (See Section 14.6 on

page 35) will result in the corresponding bit in the

DFM Interrupt Status Register (09h) (See Sec-

tion 14.10 on page 36) being set. The interrupt is

cleared by reading the DFM Interrupt Status

This feature works in all modes of operation E1 75

Ω, E1 120 Ω and T1/J1 100 Ω.

9.8 Driver Short Circuit Protection

The CS61884 provides driver short circuit protec-

tion when current on the secondary exceeds 50 mA

RMS during E1/T1/J1 operation modes.

10. RECEIVER

The CS61884 contains eight identical receivers that

utilize an internal matched impedance technique

that provides for the use of a common set of exter-

nal components for 100

Ω (T1/J1), 120 Ω (E1), and

Ω (Ε1) operation (Refer to Figure 17 on

page 51). This feature enables the use of a one

stuffing option for all E1/T1/J1 line impedances.

The appropriate E1/T1/J1 line matching is selected

via the LEN[2:0] and the CBLSEL pins in hard-

ware mode, or via the Line Length Channel ID

bits[3:0] of the Line Length Data Register (11h)

(See Section 14.18 on page 39) in host mode. The

receivers can also be configured to use different ex-

ternal resistors to match the line impedance for E1

Ω, E1 120Ω or T1/J1 100Ω modes (Refer to

Figure18 onpage52).

The CS61884 receiver provides all of the circuitry

to recover both data and clock from the data signal

input on RTIP and RRING. The matched imped-

ance receiver is capable of recovering signals with

12 dB of attenuation (referenced to 2.37 V or 3.0V

nominal) while providing superior return loss. In

addition, the timing recovery circuit along with the

jitter attenuator provide jitter tolerance that far ex-

ceeds jitter specifications (Refer to Figure 20 on

page 58).

The recovered data and clock is output from the

CS61884 on RPOS/RNEG and RCLK. These pins

output the data in one of three formats: bipolar, un-

ipolar, or RZ. The CLKE pin is used to configure

RPOS/RNEG, so that data is valid on either the ris-

ing or falling edge of RCLK.

10.1 Bipolar Output Mode

Bipolar mode provides a transparent clock/data re-

covery for applications in which the line decoding

is performed by an external framing device. The re-

covered clock and data are output on RCLK,

RNEG/BPV, and RPOS/RDATA.

10.2 Unipolar Output Mode

In unipolar mode, the CS61884 decodes the recov-

ered data with either B8ZS, HDB3 or AMI line de-

coding. The decoded data is output on the

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