CS61884 datasheet(10/72 Pages) CIRRUS

10 / 72 page

CS61884

DS485PP4

3.2 Control

SYMBOL

LQFP

FBGA

TYPE

DESCRIPTION

MCLK

Master Clock Input

This pin is a free running reference clock that should be

either 1.544 MHz for T1/J1 or 2.048 MHz for E1 operation.

This timing reference is used as follows:

- Timing reference for the clock recovery and jitter attenua-

tion circuitry.

- RCLK reference during Loss of Signal (LOS) conditions

- Transmit clock reference during Transmit all Ones (TAOS)

condition

- Wait state timing for microprocessor interface

- When this pin is held “High”, the PLL clock recovery cir-

cuit is disabled. In this mode, the CS61884 receivers

function as simple data slicers.

- When this pin is held “Low”, the receiver paths are pow-

ered down and the output pins RCLK, RPOS, and RNEG

are High-Z.

MODE

Mode Select

This pin is used to select whether the CS61884 operates in

Serial host, Parallel host or Hardware mode.

Host Mode - The CS61884 is controlled through either a

serial or a parallel microprocessor interface (Refer to HOST

MODE (See Section 13 on page 32).

Hardware Mode - The microprocessor interface is disabled

and the device control/status are provided through the pins

on the device.

NOTE: For serial host mode connect this pin to a resistor

divider consisting of two 10K

Ω resistors between

VCCIO and GNDIO.

Table 1. Operation Mode Selection

Pin State

OPERATING Mode

LOW

Hardware Mode

HIGH

Parallel Host Mode

VCCIO/2

Serial Host Mode

CS61884 датащи(PDF) 10 Page - Cirrus Logic

CS61884 датащи(HTML) 10 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL