TMS320DM6431 datasheet(87/227 Pages) TI1

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3.7.3

Pin Multiplexing Details

3.7.3.1 Multiplexed Pins on DM6431

TMS320DM6431

Digital Media Processor

www.ti.com

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-19. PINMUX1 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

–

(default).

Host Block:

GP[57]

GP[58]

GP[59]

GP[60]

GP[61]

Host Block Pin Select.

GP[62]

If EMAC opertaion is desired, EMAC must be placed in reset before

GP[63]

programminng PINMUX1 HOSTBK to select EMAC pins.

GP[64]

GP[65]

HOSTBK = 000: GPIO Mode (default).

GP[66]

Pins function as GPIO (GP[83:57]).

MCOL/GP[67]

MCRS/GP[68]

HOSTBK = 001: Reserved

MTXD3/GP[69]

6:4

HOSTBK

HOSTBK = 010: Reserved

MTXD2/GP[70]

MTXD1/GP[71]

HOSTBK = 011: Reserved

MTXD0/GP[72]

MTXCLK/GP[73]

HOSTBK = 100: MII + MDIO +10 GPIO Mode.

MRXDV/GP[74]

Pins function as MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

MTXEN/GP[75]

RXCLK, RXD[3:0]), MDIO (MDIO, MDC), and GP[66:57].

MRXER/GP[76]

MRXCLK/GP[77]

All other HOSTBK combinations reserved.

MRXD0/GP[78]

MRXD1/GP[79]

MRXD2/GP[80]

MDCLK/GP[81]

MRXD3/GP[82]

MDIO/GP[83]

Reserved. For proper device operation, the user should only write "0" to this bit

3:1

RESERVED

–

(default).

RSV

Reserved. Writes have no effect.

–

This section discusses how to program each Pin Mux Block to select the desired peripheral functions.

The following steps can be used to determine pin muxing suitable for the application:

1. Understand the major configuration choices available for the specific application.

Device Major Configuration Choices: Figure 3-10 shown in Section 3.7, Multiplexed Pin

Configurations, provides a high-level view of the device pin muxing and can be used to determine

the possible mix of peripheral options for a specific application.

EMIFA/VPSS Block Major Configuration Choices: The EMIFA/VPSS block features extensive pin

multiplexing to accommodate a variety of applications. In addition to Figure 3-10, Section 3.7.3.11,

EMIFA/VPSS Block Muxing, provides more details on the Major Configuration choices for this

block.

2. See Section 3.7.3.1, Multiplexed Pins on DM6431, for a summary of all the multiplexed pins on this

device and the pin mux group they belong to.

3. Refer to the individual pin mux sections (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11,

EMIFA/VPSS Block Muxing) for pin muxing details for a specific pin mux block.

For peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that

peripheral in all relevant pin mux blocks. For more details, see Section 3.7.3.2, Peripherals

Spanning Multiple Pin Mux Blocks.

For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2.

Table 3-20 summarizes all of the multiplexed pins on DM6431, the pin mux group for each pin, and the

PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section

(Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11, EMIFA/VPSS Block Muxing). For a description of

the PINMUX register fields, see Section 3.7.2.

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