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3.4.2

Bootmode Registers

3.4.2.1 BOOTCFG Register

TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

3.4.1.4.2 UART Boot

For UART Boot (BOOTMODE[3:0] = 1000b or 1110b), the bootloader programs the UART0 peripheral as

follows:

• UART0 divisor is set to 15

• Resulting in this UART0 baud rate in kilobit per second (kbps):

–

(CLKIN frequency in MHz) * 1000 / (15 * 16)

The user is responsible for ensuring the resulting baud rate is appropriate for the system. The UART0

divisor (/15) is optimized for CLKIN frequency between 27 to 29 MHz to stay within 5% of the 115200-bps

baud rate.

For more details on the UART peripheral configurations and clock generation, see the TMS320DM643x

DMP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (literature number SPRU997).

3.4.1.4.3 SPI Boot

Both 16-bit address SPI Boot (BOOTMODE = 0110) and 24-bit address SPI boot are performed through

the McBSP0 peripheral. The bootloader programs the McBSP0 peripheral as follows:

• McBSP0 register settings: SRGR.CLKGDV = 2

• Resulting in this SPI serial clock frequency:

–

(SYSCLK3 frequency in MHz) / 3

SYSCLK3 frequency = SYSCLK1 frequency / 6. SYSCLK1 frequency during boot can be found in

Table 3-5, Table 3-6, Table 3-7, and/or Table 3-8 based on the boot mode selection.

For example, if BOOTMODE[3:0] = 0110b, FASTBOOT = 1, the MXI/CLKIN frequency = 27 MHz,

AEM[2:0] = 000b, PLLMS[2:0] = 100b, the combination of Table 3-7 and Table 3-8 indicates that the

device frequency (SYSCLK1) is CLKIN x 22 / 2 = 297 MHz. This means SYSCLK3 frequency is

297 / 6 = 49.5 MHz, resulting in SPI serial clock frequency of 49.5 / 3 = 16.5 MHz.

The Device Bootmode (see Section 3.4.1, Boot Modes) and Configuration pins (see Section 3.5.1, Device

and Peripheral Configurations at Device Reset) latched at reset are captured in the Device Boot

Configuration (BOOTCFG) register which is accessible through the System Module. This is a read-only

reset. For more information on how these pins are sampled at device reset, see Section 6.5.1.2, Latching

Boot and Configuration Pins. For the corresponding device boot and configuration pins, see Table 2-5,

BOOT Terminal Functions.

RESERVED

FASTBOOT

RESERVED

R-0000 0000 0001

R-L

R-000

RSV

PLLMS

RSV

DAEM

RESERVED

BOOTMODE

R-0

R-LLL

R-0

R-LLL

R-0000

R-LLLL

LEGEND: R = Read only; L = pin state latched at reset rising edge; -n = value after reset

Figure 3-3. BOOTCFG Register—0x01C4 0014

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