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3.5 Configurations At Reset

3.5.1

Device and Peripheral Configurations at Device Reset

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Some device configurations are determined at reset. The following subsections give more details.

Table 2-5, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device

reset for configuring basic device settings for proper device operation. Table 3-12, summarizes the device

boot and configuration pins, and the device functions that they affect.

Table 3-12. Default Functions Affected by Device Boot and Configuration Pins

DEVICE BOOT AND

CONFIGURATION

BOOT SELECTED

PIN MUX CONTROL

GLOBAL SETTING

PERIPHERAL SETTING

PINS(1)

BOOTMODE[3:0]

Boot Mode

PINMUX0/PINMUX1

I/O Pin Power:

PSC/Peripherals:

Registers:

Based on

BOOTMODE[3:0], the

bootloader code programs bootloader code programs

bootloader code programs VDD3P3V_PWDN register the PSC to put

PINMUX0 and PINMUX1

to power up the I/O pins

boot-related peripheral(s)

registers to select the

required for boot.

in the Enable State, and

appropriate pin functions

programs the peripheral(s)

required for boot.

for boot operation.

FASTBOOT

Fastboot

–

Sets Device Frequency:

–

Based on BOOTMODE,

FASTBOOT, PLLMS, and

AEM the bootloader code

programs PLLC1.

AEAW[2:0]/PLLMS[2:0]

If FASTBOOT = 1 and

PINMUX0.AEAW:

Sets Device Frequency:

–

AEM = 000b or 101b the

AEAW[2:0] sets the

Based on BOOTMODE,

PLLMS[2:0] selects the

default of this field to

FASTBOOT, PLLMS, and

FASTBOOT PLL

control the EMIFA

AEM the bootloader code

Multiplier.

address bus width (only

programs PLLC1.

applicable if

PINMUX0.AEM = 001b).

Affects the pin muxing in

EMIFA/VPSS Sub-Block

AEM[2:0]

Together with FASTBOOT PINMUX0.AEM:

Sets Device Frequency:

PSC/EMIFA:

and PLLMS[2:0] ,

Sets the default of this

Based on BOOTMODE,

The EMIFA module state

determines the

field to control the EMIFA

FASTBOOT, PLLMS, and

defaults to SwRstDisable

FASTBOOT PLL

Pinout Mode.

AEM the bootloader code

if AEM = 0; otherwise, the

Multiplier.

programs PLLC1.

EMIFA module state

Affects the pin muxing in

defaults to Enable.

EMIFA/VPSS Sub-Block

0, 1, and 3.

(1)

Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults.

For proper device operation, external pullup/pulldown resistors may be required on these device boot and

configuration pins. For discussion situations where external pullup/pulldown resistors are required, see

Section 3.9.1, Pullup/Pulldown Resistors.

Note: All DM6431 configuration inputs (BOOTMODE[3:0], FASTBOOT, AEAW[2:0]/PLLMS[2:0] and

AEM[2:0]) are multiplexed with other functional pins. These pins function as device boot and configuration

pins only during device reset. The user must take care of any potential data contention in the system. To

help avoid system data contention, the DM6431 puts these configuration pins into a high-impedance state

(Hi-Z) when device reset (RESET or POR) is asserted, and continues to hold them in a high-impedance

state until the internal global reset is removed; at which point, the default peripheral (either GPIO or

EMIFA based on default of AEM[2:0]) will now control these pins.

All of the device boot and configuration pin settings are captured in the corresponding bit fields in the

BOOTCFG register (see Section 3.4.2.1).

Device Configurations

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