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HT69F360 датащи(PDF) 151 Page - Holtek Semiconductor Inc |
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HT69F360 датащи(HTML) 151 Page - Holtek Semiconductor Inc |
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151 / 235 page ![]() Rev. 1.30 150 �ove��e� 1�� �01� Rev. 1.30 151 �ove��e� 1�� �01� HT69F340/HT69F350/HT69F360 TinyPowerTM I/O Flash MCU with LCD & EEPROM HT69F340/HT69F350/HT69F360 TinyPowerTM I/O Flash MCU with LCD & EEPROM Bit0 TRF:SPITransmit/ReceiveCompleteflag 0:Dataisbeingtransferred 1:SPIdatatransmissioniscompleted TheTRFbitistheTransmit/ReceiveCompleteflagandisset“1”automaticallywhen anSPIdatatransmissioniscompleted,butmustsetto“0”bytheapplicationprogram. Itcanbeusedtogenerateaninterrupt. SPI Communication AftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,when dataiswrittentotheSIMDregister,transmission/receptionwillbeginsimultaneously.Whenthe datatransferiscomplete,theTRFflagwillbesetautomatically,butmustbeclearedusingthe applicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived, anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedinto theSIMDregister.ThemastershouldoutputaSCSsignaltoenabletheslavedevicebeforeaclock signalisprovided.Theslavedatatobetransferredshouldbewellpreparedattheappropriate momentrelativetotheSCSsignaldependingupontheconfigurationsoftheCKPOLBbitandCKEG bit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignal forvariousconfigurationsoftheCKPOLBandCKEGbits.TheSPIwillcontinuetofunctioneven intheIDLEMode. SC K (C KP OL B= 1, C KE G= 0) SI ME N, C SE N= 1 SI ME N= 1, C SE N= 0 (E xt er nal P ul l- Hi gh ) SC K (C KP OL B= 0 , C KE G= 0) SC K (C KP OL B= 1 , C KE G= 1) SC K (C KP OL B= 0 , C KE G= 1) SD O (C KE G= 0) SD O (C KE G= 1) SC S SD I Da ta C apt ur e D7 /D 0D 6/ D1 D5 /D 2D 4/ D3 D3 /D 4D 2/ D5 D1 /D 6D 0/ D7 D7 /D 0D 6/ D1 D5 /D 2D 4/ D3 D3 /D 4D 2/ D5 D1 /D 6D 0/ D7 Wr it e to S IM D SPI Master Mode Timing SC K (C KP OL B= 1) SC K (C KP OL B= 0) SD O SC S SD I Da ta C apt ur e D7 /D 0D 6/ D1 D5 /D 2D 4/ D3 D3 /D 4D 2/ D5 D1 /D 6D 0/ D7 Wr it e to S IM D (S DO d oe s not c hange un ti l fi rs t SC K edge ) SPI Slave Mode Timing – CKEG=0 |
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