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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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S3A3 датащи(PDF) 124 Page - Renesas Technology Corp |
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S3A3 датащи(HTML) 124 Page - Renesas Technology Corp |
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124 / 139 page  R01DS0307EU0100 Rev.1.00 Page 124 of 139 Mar 7, 2017 S3A3 2. Electrical Characteristics Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. 2.16 Boundary Scan Note 1. Boundary scan does not function until power-on-reset becomes negative. Figure 2.93 Boundary scan TCK timing Table 2.80 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 5.5 V, Ta = –40 to +85°C Parameter Symbol FCLK = 4 MHz FCLK = 8 MHz Unit Min Typ Max Min Typ Max Programming time 1-byte tDP1 - 94.7 886 - 89.3 849 μs Erasure time 1-KB tDE1K - 9.59 299 - 8.29 273 ms Blank check time 1-byte tDBC1 - - 56.2 - - 52.5 μs 1-KB tDBC1K - - 2.17 - - 1.51 ms Suspended time during erasing tDSED - - 23.0 - - 21.7 μs Data flash STOP recovery time tDSTOP 720 - - 720 - - ns Table 2.81 Boundary scan Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 100 - - ns Figure 2.93 TCK clock high pulse width tTCKH 45 - - ns TCK clock low pulse width tTCKL 45 - - ns TCK clock rise time tTCKr -- 5 ns TCK clock fall time tTCKf -- 5 ns TMS setup time tTMSS 20 - - ns Figure 2.94 TMS hold time tTMSH 20 - - ns TDI setup time tTDIS 20 - - ns TDI hold time tTDIH 20 - - ns TDO data delay tTDOD - - 70 ns Boundary Scan circuit start up time*1 tBSSTUP tRESWP -- - Figure 2.95 tTCKcyc tTCKH tTCKf tTCKL tTCKr TCK |
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