S3A3 datasheet(85/139 Pages) RENESAS

85 / 139 page

R01DS0307EU0100 Rev.1.00

Page 85 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

Note 1.

tPcyc: PCLKA cycle.

Note 2.

N is set as an integer from 1 to 8 by the SPCKD register.

Note 3.

N is set as an integer from 1 to 8 by the SSLND register.

Note 4.

The upper limit of RSPCK is 16 MHz.

SPI

Data output delay

Master

2.7 V or above

tOD

-14

Figure 2.62 to

Figure 2.67

2.4 V or above

1.8 V or above

1.6 V or above

Slave

2.7 V or above

2.4 V or above

1.8 V or above

1.6 V or above

110

Data output hold

time

Master

tOH

Slave

Successive

transmission delay

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc

+ 2 × tPcyc

Slave

6 × tPcyc

MOSI and MISO

rise and fall time

Output

2.7 V or above

tDr, tDf

-10

2.4 V or above

1.8 V or above

1.6 V or above

Input

µs

SSL rise and fall

time

Output

2.7 V or above

tSSLr,

tSSLf

-10

2.4 V or above

1.8 V or above

1.6 V or above

Input

µs

Slave access time

2.4 V or above

tSA

-2 × tPcyc + 100 ns

Figure 2.66 and

Figure 2.67

1.8 V or above

2 × tPcyc + 140

1.6 V or above

2 × tPcyc + 180

Slave output release time

2.4 V or above

tREL

-2 × tPcyc + 100 ns

1.8 V or above

2 × tPcyc + 140

1.6 V or above

2 × tPcyc + 180

Table 2.40

SPI timing (2 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register

Parameter

Symbol

Min

Max

Unit*1

Test conditions

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