S3A3 datasheet(95/139 Pages) RENESAS

номер детали	S3A3

подробное описание детали	Microcontroller

PDF	139 Pages

Scroll/Zoom	100%

производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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95 / 139 page

R01DS0307EU0100 Rev.1.00

Page 95 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

Figure 2.74

SSIE data output delay from SSILRCK0/SSIFS0 change time

2.3.14

SD/MMC Host Interface Timing

Figure 2.75

SD/MMC host interface signal timing

Table 2.44

SD/MMC host interface signal timing

Conditions: VCC = 2.7 to 5.5 V

Middle drive output is selected in the Port Drive Capability in PmnPFS register

Parameter

Symbol

Min

Max

Unit

Test

conditions

SDCLK clock cycle

tSDCYC

62.5

Figure 2.75

SDCLK clock high-level pulse width

tSDWH

18.25

SDCLK clock low-level pulse width

tSDWL

18.25

SDCLK clock rising time

tSDLH

-10

SDCLK clock falling time

tSDHL

-10

SDCMD/SDDAT output data delay

tSDODLY

–18.25

18.25

SDCMD/SDDAT input data setup

tSDIS

9.25

SDCMD/SDDAT input data hold

tSDIH

23.25

tDTRW

SSILRCK0/SSIFS0 (Input)

SSITXD0 (Output)

MSB bit output delay from SSILRCK0/SSIFS0 change time for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]

SDCLK

(output)

SDCMD/SDDAT

(input)

SDCMD/SDDAT

(output)

tSDODLY(max)

tSDIS

tSDIH

tSDLH

tSDHL

tSDCYC

tSDWH

tSDWL

tSDODLY(min)

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