S3A3 datasheet(48/139 Pages) RENESAS

48 / 139 page

R01DS0307EU0100 Rev.1.00

Page 48 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

Note 1.

Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up

MOSs are in the off state.

Note 2.

The clock source is HOCO.

Note 3.

The clock source is MOCO.

Note 4.

The clock source is the sub-clock oscillator.

Note 5.

This does not include BGO operation.

Note 6.

This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution.

Note 7.

FCLK, BCLK, PCLKA, PCLKB, PCLKC and PCLKD are set to divided by 64.

Note 8.

FCLK, BCLK, PCLKA, PCLKB, PCLKC and PCLKD are the same frequency as that of ICLK.

Note 9.

FCLK, BCLK, and PCLKB are set to divided by 2 and PCLKA, PCLKC and PCLKD are the same frequency as that of ICLK.

Note 10. VCC = 3.3 V.

Supply

current

Low-speed

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 1 MHz

ICC

0.4

All peripheral clock

disabled, CoreMark code

executing from flash

ICLK = 1 MHz

0.6

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 1 MHz

1.1

All peripheral clock

enabled, code executing

from SRAM

ICLK = 1 MHz

2.5

Sleep mode

All peripheral clock

disabled

ICLK = 1 MHz

0.3

All peripheral clock

enabled

ICLK = 1 MHz

1.0

Low-voltage

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 4 MHz

ICC

1.8

All peripheral clock

disabled, CoreMark code

executing from flash

ICLK = 4 MHz

3.0

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 4 MHz

3.3

All peripheral clock

enabled, code executing

from SRAM

ICLK = 4 MHz

9.0

Sleep mode

All peripheral clock

disabled

ICLK = 4 MHz

1.4

All peripheral clock

enabled

ICLK = 4 MHz

2.9

Subosc-

speed

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 32.768 kHz

ICC

9.3

μA

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 32.768 kHz

17.2

All peripheral clock

enabled, code executing

from SRAM

ICLK = 32.768 kHz

106.0

Sleep mode

All peripheral clock

disabled

ICLK = 32.768 kHz

6.0

All peripheral clock

enabled

ICLK = 32.768 kHz

14.0

Table 2.11

Operating and standby current (1) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Typ*10

Max

Unit

Test

conditions

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