S3A3 datasheet(56/139 Pages) RENESAS

56 / 139 page

R01DS0307EU0100 Rev.1.00

Page 56 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

2.3

AC Characteristics

2.3.1

Frequency

Note 1.

The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer

frequency such as 1.5 MHz cannot be set.

Note 2.

The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency

accuracy of the clock source.

Note 3.

The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in

use.

Note 4.

See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK, and BCLK.

Note 5.

The maximum value of operation frequency does not include the internal oscillator errors. The operation can be guaranteed

with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.22, Clock timing.

Table 2.17

Operation frequency value in high-speed operating mode

Conditions: VCC = AVCC0 = 2.4 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*4

2.7 to 5.5 V

0.032768

MHz

2.4 to 2.7 V

0.032768

FlashIF clock (FCLK)*1, *2, *4

2.7 to 5.5 V

0.032768

2.4 to 2.7 V

0.032768

Peripheral module clock (PCLKA)*4

2.7 to 5.5 V

2.4 to 2.7 V

Peripheral module clock (PCLKB)*4

2.7 to 5.5 V

2.4 to 2.7 V

Peripheral module clock (PCLKC)*3, *4

2.7 to 5.5 V

2.4 to 2.7 V

Peripheral module clock (PCLKD)*4

2.7 to 5.5 V

2.4 to 2.7 V

External bus clock (BCLK)*4

2.7 to 5.5 V

2.4 to 2.7 V

EBCLK pin output

2.7 to 5.5 V

2.4 to 2.7 V

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