REV. 0

ADV7183

–31–

Table XXXVI. Auto Clock Control Register (Subaddress 2B)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

RESERVED

00000

Set to Zero

ACLKN[2:0]

*

0

0

0

Color Burst Line

0

0

1

Start Line 24 Color Burst Line

0

1

0

Active Video

0

1

1

Active Video (<304) PAL, (<264) NTSC

1

0

0

Active Video (<304) PAL, (<256) NTSC

1

0

1

Active Video (<319/320) PAL, (<273/274) NTSC

1

1

0

Invalid

1

1

1

Invalid

*Automatic Clock Generator Mode. Influences the mode of operation for the LLC. Only when not in Manual Mode.

Table XXXVII. AGC Mode Control Register (Subaddress 2C)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

CAGC[1:0]

1

0

0

Manual Fixed Gain; use CMG [11:0]

0

1

Use Luma Gain for Chroma

1

0

Automatic Gain; Based on Color Burst

1

1

Freeze Chroma Gain

RESERVED

1

1

Set to One

LAGC[2:0]

2

000

Manual Fixed Gain

3

0

0

1

AGC No Override through White Peak; Manual IRE

0

1

0

AGC Auto Override through White Peak; Manual

IRE Control

4

0

1

1

AGC No Override through White Peak; Manual IRE

Control

4

1

0

0

AGC Auto Override through White Peak; Manual

IRE Control

4

1

0

1

AGC Active Video with White Peak

1

1

0

AGC Active Video with Average Video

1

1

1

Freeze Gain

RESERVED

1

Set to One

NOTES

Table XXXVIII. Chroma Gain Control 1 Register (Subaddress 2D)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

CMG[11:8]

1

XXXX

RESERVED

1

1

Set to One

CAGT[1:0]

2

0

0

Slow (TC = 2 sec)

01

Medium (TC = 1 sec)

10

Fast (TC = 0.2 sec)

11

Dependent on VID_QUAL

NOTES

CMG[11:0] will operate.

Table XXXIX. Chroma Gain Control 2 Register (Subaddress 2E)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

CMG[7:0]

*

XXXXXXXX

*Chroma Manual Gain. Lower 8 bits, see CMG [11:8] for description.