AD7183 datasheet(24/40 Pages) AD

24 / 40 page

REV. 0

–24–

ADV7183

Table IX. Extended Output Control Register (Subaddress 04)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

RANGE

CCIR-Compliant

Fill Whole Accessible Range

RESERVED

110

DDOS[2:0]

000

No Additional Data

BT656-4

BT656-3-Compatible

BT656-4-Compatible

NOTES

1Allows the user to select the range of output values. Can be CCIR601-compliant or fill the whole accessible number range.

2D Data Output Selection. If the 100-pin package is used, the 12 additional pins can output additional data.

312 Pins Three-State

4Allows the user to select an output mode that is compatible with BT656-4 or BT656-3.

Table X. General-Purpose Output Register (Subaddress 05)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

GPO[3:0]

0000

User Programmable

HD Test Pattern Off

GPEL

GPO[1:0] Three-Stated

GPO[1:0] Enabled

GPEH

GPO[3:2] Three-Stated

GPO[3:2] Enabled

BL_C_VBI

Decode and Output Color During VBI

Blank Cr and Cb Data During VBI

HL_EN

GPO[0] Pin Function6

GPO[0] Shows HLOCK Status6

NOTES

1Pixel Data Valid Off. These general-purpose output pins may be programmed by the user but are only available in selected output modes OF_SEL[3:0] and when the

output drivers are enabled using GPEL, GPEH, and HL_Enable bits.

2General Purpose Enable Low. Enables the output drivers for the general-purpose outputs Bits 0 and 1.

3General Purpose Enable High. Enables the output drivers for the general-purpose outputs Bits 2 and 3.

4Blank Chroma During VBI.

5Hlock Enable. This bit causes the GPO[0] pin to output Hlock instead of GPO[0]. Only available in certain output modes.

6GPO lower bits must be enabled GPEL. Disabled.

Table XI. FIFO Control Register (Subaddress 07)

Bit Description

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting

FFM[4:0]

00100

User Programmable

Normal Operation

FIFO Reset

AFR

No Auto Reset

Auto Reset

FFST

Synchronous to CLKIN

Synchronous to 27 MHz

NOTES

1FIFO Flag Margin. Allows the user to program the location at which the FIFO flags AEF and AFF.

2FIFO Reset. Setting this bit will cause the FIFO to reset.

3Bit is auto cleared.

4Automatic FIFO Reset. Setting this bit will cause the FIFO to automatically reset at the end of each field of video.

5FIFO Flag Self Time. Sets whether the FIFO flags AEF, AFF, and HFF are output synchronous to the external CLKIN of the 27 MHz internal clock.

Table XII. Contrast Register (Subaddress 08)

Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

CON[7:0]

10000000

*Contrast Adjust. This is the user control for contrast adjustment.

AD7183 датащи(PDF) 24 Page - Analog Devices

AD7183 датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL