AD7183 datasheet(14/40 Pages) AD

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ADV7183

OUTPUT INTERFACE

Mode Selection Overview

The ADV7183 supports three output interfaces: LLC-compatible

synchronous pixel interface, the CAPI interface, and the SCAPI

interface. When the part is configured in the synchronous pixel

interface mode, pixel and control data are output synchronous with

LLC1 (8-bit mode) or LLC2 (16-bit mode). In this mode control

and timing information for field, vertical blanking, and horizontal

blanking identification may also be encoded as control codes.

When configured in CAPI or SCAPI mode only the active

pixel data is output synchronous with the CLKIN (asynchronous

FIFO clock). The pixels are output via a 512-pixel deep, 20-bit

wide FIFO. HACTIVE and VACTIVE are output on independent

pins. HACTIVE will be active during the active viewable period

of a video line and VACTIVE will be active during the active

viewable period of a video field. CAPI and SCAPI modes will

always output data in 16-bit, so this mode of operation cannot be

used when an 8-bit or 10-bit output interface is required. After

power-up, the ADV7183 will default to the LLC-compatible

8-bit CCIR656 4:2:2 @ LLC.

Synchronous Pixel Interface

When the output is configured for an 8-bit pixel interface, the

data is output on the pixel output port P[15:8]. In this mode,

8 bits of chrominance data will precede 8 bits of luminance

data. New pixel data is output on the pixel port after each

rising edge of LLC1. When the output is configured for a 16-

bit pixel interface, the luminance data is output on P[15:8]

and the chrominance data on P[7:0]. In this mode the data is

output with respect to LLC2. Figure 20 shows the basic timing

relationship for this mode.

PIXEL DATA

SAV

P15-8[7:0]

LLC1

LLC2

PIXEL DATA

P7-0[7:0]

SAV

Cb0

Cr0

Cb1

Cr1

Cb2

Figure 20. Synchronous Pixel Interface, 16-Bit Example

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