AD7183 datasheet(19/40 Pages) AD

19 / 40 page

REV. 0

ADV7183

–19–

The MPU can write to or read from all of the registers of the

ADV7183 except the subaddress register, which is a write only

next read or write operation accesses. All communications with

the part through the bus start with an access to the subaddress

target address which then increments to the next address until a

stop command on the bus is performed.

The following section describes each register in terms of its

configuration.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write only register. After the

part has been accessed over the bus and a read/write operation is

selected, the subaddress is set up. The subaddress register

determines to/from which register the operation takes place.

Table II shows the various operations under the control of the

subaddress register. Zero should always be written to SR7–SR6.

These bits are set up to point to the required starting address.

Addr (Hex)

BASIC BLOCK

Input Control

Video Selection

Video Enhancement Control

Output Control

Extended Output Control

General-Purpose Output

Reserved

FIFO Control

Contrast Control

Saturation Control

Brightness Control

Hue Control

Default Value Y

Default Value C

Temporal Decimation

Power Management

Status Register

Info Register

Addr (Hex)

ADVANCED BLOCK

Reserved

Analog Control (Internal)

Analog Clamp Control

Digital Clamp Control 1

Digital Clamp Control 2

Shaping Filter Control

Reserved

Comb Filter Control

Reserved

Color Subcarrier Control 1

Color Subcarrier Control 2

Color Subcarrier Control 3

Color Subcarrier Control 4

Pixel Delay Control

Manual Clock Control 1

Manual Clock Control 2

Manual Clock Control 3

Auto Clock Control

AGC Mode Control

Chroma Gain Control 1

Chroma Gain Control 2

Luma Gain Control 1

Luma Gain Control 2

Manual Gain Shadow Control 1

Manual Gain Shadow Control 2

Misc Gain Control

HSync Position Control 1

HSync Position Control 2

HSync Position Control 3

Polarity Control

Reserved

SDATA

SCLOCK

1–78

START ADDR R/

W ACK SUB ADDR

ACK

DATA

ACK

STOP

Figure 29. Bus Data Transfer

Table II. Subaddress Register

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