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STM8L101x2 датащи(PDF) 41 Page - STMicroelectronics |
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STM8L101x2 датащи(HTML) 41 Page - STMicroelectronics |
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41 / 88 page ![]() DocID15275 Rev 16 41/88 STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters 63 9.3.2 Power-up / power-down operating conditions 9.3.3 Supply current characteristics Total current consumption The MCU is placed under the following conditions: • All I/O pins in input mode with a static value at VDD or VSS (no load) • All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD and TA. Table 17. Operating conditions at power-up / power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 20 - 1300 µs/V tTEMP Reset release delay VDD rising - 1 - ms VPOR(1)(2) 1. Guaranteed by characterization results. 2. Correct device reset during power on sequence is guaranteed when tVDD[max] is respected. External reset circuit is recommended to ensure correct device reset during power down, when VPDR < VDD < VDD[min]. Power on reset threshold - 1.35 - 1.65(3) 3. Tested in production. V VPDR(1)(2) Power down reset threshold - 1.40 - 1.60 V |
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