STM8L101X2 datasheet(86/88 Pages) STMICROELECTRONICS

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Revision history

STM8L101x1 STM8L101x2 STM8L101x3

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DocID15275 Rev 16

14-Oct-2010

Added STM8L101F1 devices:

Modified Table 1: Device summary on page 1, Table 2:

STM8L101xx device feature summary on page 9 and Table 5:

Flash and RAM boundary addresses on page 24

Modified warning below Figure 3 on page 16 and belowTable 4:

STM8L101xx pin description on page 20

Modified Figure 52: STM8L101xx ordering information scheme on

page 79

Modified text above Figure 32: Recommended NRST pin

configuration on page 54

Modified Figure 32 on page 54

02-Aug-2013

Added “The RAM content is preserved” in halt mode Section 3.6:

Low power modes

Reformatted Figure 2: Standard 20-pin UFQFPN package pinout,

Figure 3: 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers,

Figure 4: 20-pin TSSOP package pinout, Figure 4: 20-pin TSSOP

package pinout, Figure 5: Standard 28-pin UFQFPN package pinout,

Figure 6: 28-pin UFQFPN package pinout for STM8L101G3U6ATR

and STM8L101G2U6ATR part numbers and Figure 7: 32-pin

package pinout

Corrected NRST/PA1 pin OD output capability in Table 4:

STM8L101xx pin description and corrected note 2. and 4.

Added note “Slope control of all GPIO can be programmed except...”

in Table 4: STM8L101xx pin description

Added note under Table 5: Flash and RAM boundary addresses

Replaced UM0320 with UM0470 in Section 7: Option bytes

Updated OPT2 and OPT3 in Table 10: Option bytes

Added additional note 2. references in Table 22: HSI oscillator

characteristics

Added note 2. under Table 17: Operating conditions at power-up /

power-down and under Figure 32: Recommended NRST pin

configuration

Corrected ‘SCK output’ in Figure 35: SPI timing diagram - master

mode(1)

Added top view in Figure 43: UFQFPN20 3 x 3 mm 0.6 mm package

outline

Repositioned the package layout and footprint for all packages.

Replaced “Standard ports” with “High sink ports”

Replaced “TIMx_TRIG” with “TIMx_ETR”

Replaced all ‘"Data guaranteed, each individual device tested in

production” notes with “Tested in production”

31-Mar-2014

Updated L3 value on Table 42, added note 2) and 3) on Table 43

18-Dec-2014

Updated:

– Figure 46: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin

fine pitch quad flat package outline,

– Table 42: UFQFPN20 - 20-lead ultra thin fine pitch quad flat

package (3 x 3 mm) mechanical data.

Table 44. Document revision history (continued)

Date

Revision

Changes

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