ST72344K2 datasheet(222/247 Pages) STMICROELECTRONICS

222 / 247 page

Electrical characteristics

ST72344xx, ST2345xx

222/247

Doc ID 12321 Rev 6

Figure 114. Typical VDD – VOH vs. VDD (high sink)

13.10

Control pin characteristics

13.10.1

Asynchronous RESET pin

TA = -40 °C to 85 °C, unless otherwise specified.

120

160

200

2.533.5

Ilo (mA)

-45°C

25°C

90°C

130°C

100

200

300

400

500

2.533.5

Ilo (mA)

-45°C

25°C

90°C

130°C

Table 109.

Asynchronous RESET pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

Vss - 0.3

0.3VDD

VIH

Input high level voltage

0.7VDD

VDD + 0.3

Vhys

Schmitt trigger voltage

hysteresis (1)

Data based on characterization results, not tested in production.

VOL

Output low level voltage (2)

The IIO current sunk must always respect the absolute maximum rating specified in Table 85: Current

characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

VDD = 5 V

IIO = +5 mA

0.5

1.0

IIO = +2 mA

0.2

0.4

RON

Pull-up equivalent resistor

(3)(1)

The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin

between VILmax and VDD

VDD = 5 V

VDD = 3 V

120

tw(RSTL)out

Generated reset pulse

duration

Internal reset sources

14 (1)

µs

th(RSTL)in

External reset pulse hold

time (4)

To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses

applied on RESET pin with a duration below th(RSTL)in can be ignored.

12 (1)

µs

tg(RSTL)in

Filtered glitch duration

200

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