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ST72344K2 датащи(PDF) 212 Page - STMicroelectronics

номер детали ST72344K2
подробное описание детали  SCI asynchronous serial interface
PDF  247 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST72344K2 датащи(HTML) 212 Page - STMicroelectronics

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Electrical characteristics
ST72344xx, ST2345xx
212/247
Doc ID 12321 Rev 6
13.7
Memory characteristics
TA = –40°C to 85°C, unless otherwise specified.
Table 100.
RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode (1)
1.
Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
Halt mode (or reset)
1.6
V
Table 101.
Flash program memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Operating voltage for
Flash write/erase
Refer to operating range of
VDD with TA, Table 87
2.7
5.5
V
tprog
Programming time for
1~32 bytes (1)
1.
Up to 32 bytes can be programmed at a time.
TA=−40 to +85°C
5
10
ms
tRET
Data retention (2)
2.
Data based on reliability test results and monitored in production.
TA=+55°C
(3)
3.
The data retention time increases when the TA decreases.
20
years
NRW
Write erase cycles
TA=+25°C
10,000
(4)
4.
Design target value pending full product characterization.
cycles
IDD
Supply current (5)
5.
Guaranteed by Design. Not tested in production.
Read / Write / Erase modes
fCPU = 8 MHz, VDD = 5.5V
2.6
mA
No Read/No Write Mode
100
µA
Power down mode / Halt
0
0.1
µA
Table 102.
EEPROM data memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Operating voltage for
EEPROM write/erase
Refer to operating range of
VDD with TA, Table 87:
General operating conditions
2.7
5.5
V
tprog
Programming time for
1~32 bytes
TA=−40 to +85°C
5
10
ms
tret
Data retention(1)
1.
Data based on reliability test results and monitored in production.
TA=+55°C
(2)
2.
The data retention time increases when the TA decreases.
20
years
NRW
Write erase cycles
TA=+25°C
300,000
(3)
3.
Design target value pending full product characterization.
cycles



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